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Energy-efficient redundant execution for chip multiprocessors

Pramod Subramanyan, Virendra Singh, Kewal K. Saluja, Erik Larsson
2010 Proceedings of the 20th symposium on Great lakes symposium on VLSI - GLSVLSI '10  
In this paper, we describe a power-efficient architecture for redundant execution on chip multiprocessors (CMPs) which when coupled with our per-core dynamic voltage and frequency scaling (DVFS) algorithm  ...  significantly reduces the energy overhead of redundant execution without sacrificing performance.  ...  In this paper, we showed the design of an energy-efficient faulttolerant microarchitecture for chip multiprocessors.  ... 
doi:10.1145/1785481.1785516 dblp:conf/glvlsi/SubramanyanSSL10 fatcat:eknbfiqe6fa4rb5pe5n4o2jqky

Exploring chip-multiprocessors in deeply-embedded real-time computing

Xuan Qi
2008 ACM SIGBED Review  
As an energy efficient high-performance architecture, chip multiprocessor (CMP) can be deployed in deeply-embedded real-time computing.  ...  I discuss the issues to be addressed such as effective resource modeling, efficient scheduling algorithms, and energy efficient design.  ...  , energy efficiency and high reliability.  ... 
doi:10.1145/1366283.1366296 fatcat:p6f3gmhxrvfsncsd43ov6vk7ti

Power-Efficient Error Tolerance in Chip Multiprocessors

M.W. Rashid, E.J. Tan, M.C. Huang, D.H. Albonesi
2005 IEEE Micro  
We divide a computation into a series of chunks and run them on two or more copies of the same hardware to achieve the same processing bandwidth as a sequential execution at a more energy-efficient operating  ...  We base our approach on a CMP microarchitecture (it therefore most closely resembles chip-level redundant threading, or CRT 5 ).  ...  We have described a flexible platform using novel mechanisms and modest hardware support to enable on-demand, energy-efficient redundant execution.  ... 
doi:10.1109/mm.2005.118 fatcat:avxnsxsuprdcvltlt7omljv7nu

On-chip sensor networks for soft-error tolerant real-time multiprocessor systems-on-chip

Weichen Liu, Xuan Wang, Jiang Xu, Wei Zhang, Yaoyao Ye, Xiaowen Wu, Mahdi Nikdast, Zhehui Wang
2014 ACM Journal on Emerging Technologies in Computing Systems  
On-chip sensor networks for soft-error tolerant real-time multiprocessor systems-on-chip.  ...  State-of-the-art techniques for soft error protections targeting multiprocessor systems result either high chip cost and area overhead or high performance degradation and energy consumption, and do not  ...  The items of energy consumed by the respective on-chip components are combined for clarity.  ... 
doi:10.1145/2564928 fatcat:66r4x436rfh2jhx7olz6tbcrqy

Adaptive execution assistance for multiplexed fault-tolerant chip multiprocessors

Pramod Subramanyan, Virendra Singh, Kewal K. Saluja, Erik Larsson
2011 2011 IEEE 29th International Conference on Computer Design (ICCD)  
In this paper, we introduce a new throughput-efficient architecture for multiplexed fault-tolerant chip multiprocessors (CMPs).  ...  Through simulation-based evaluation, we find that our proposal delivers 17.2% higher throughput than perfect dual modular redundant (DMR) execution and outperforms previous proposals for throughput-efficient  ...  RECVF [35] introduced the technique of critical value forwarding and showed how it could be exploited for energy-efficient redundant execution.  ... 
doi:10.1109/iccd.2011.6081432 dblp:conf/iccd/SubramanyanSSL11 fatcat:bv453zeg4jbo5pzeuckhvp26bi

Multiplexed redundant execution: A technique for efficient fault tolerance in chip multiprocessors

Pramod Subramanyan, Virendra Singh, Kewal K Saluja, Erik Larsson
2010 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)  
To mitigate the effect of decreased reliability, a number of fault-tolerant architectures have been proposed that exploit the natural coarse-grained redundancy available in chip multiprocessors (CMPs).  ...  Consequently a CMP which is capable of executing 2n threads in non-redundant mode can only execute half as many (n) threads in fault-tolerant mode.  ...  Although this improves energy efficiency of redundant execution, it does not affect the throughput loss. SRT and SRTR execute the leading and trailing threads on the same core.  ... 
doi:10.1109/date.2010.5457061 dblp:conf/date/SubramanyanSSL10 fatcat:5lewxc7obvfdjff7kapemj43tq

A Survey on Scheduling Approaches for Hard Real-Time Systems

Mehrin Rouhifar, Reza Ravanmehr
2015 International Journal of Computer Applications  
Second part contains the different heuristic and partitioned approaches for some specific factors of real-time systems such as energy consumption, dependability, performance, scheduling feasibility and  ...  Finally, the analysis and evaluation of the mentioned methods are shown based on the schedulability of task sets and efficiency.  ...  with rollback recovery for time-based redundancy.  ... 
doi:10.5120/ijca2015907656 fatcat:na7u3dgqsjhphl253ecd22jkau

Tuning data replication for improving behavior of MPSoC applications

O. Ozturk, M. Kandemir, M. J. Irwin, I. Kolcu
2004 Proceedins of the 14th ACM Great Lakes symposium on VLSI - GLSVLSI '04  
Maintaining cache coherence can be very costly for on-chip multiprocessors from an energy perspective.  ...  The goal is to eliminate the energy costs associated with bus snooping without negatively impacting overall performance.  ...  ., with no speculation/predication logic for example), this architecture is also energy efficient.  ... 
doi:10.1145/988952.988994 dblp:conf/glvlsi/OzturkKIK04 fatcat:w35sv54d5zbjdlc36m5jywsib4

A new direction for computer architecture research

C.E. Kozyrakis, D.A. Patterson
1998 Computer  
computing domains that have shaped processor architecture for the past decade: • The uniprocessor desktop running technical and scientific applications, and • the multiprocessor server used for transaction  ...  Seven articles from academic research groups proposed microprocessor architectures and implementations for billion-transistor chips.  ...  In addition, we thank the following for their useful feedback, comments, and criticism on earlier drafts, as well as the grades for vector IRAM: Anant Agarwal  ... 
doi:10.1109/2.730733 fatcat:ykv5f53p5rfdfo4a72a4i25g2q

Total Energy Minimization of Real-Time Tasks in an On-Chip Multiprocessor Using Dynamic Voltage Scaling Efficiency Metric

Hyunjin Kim, Hyejeong Hong, Hong-Sik Kim, Jin-Ho Ahn, Sungho Kang
2008 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
This paper proposes an algorithm that provides both dynamic voltage scaling and power shutdown to minimize the total energy consumption of an application executed on an on-chip multiprocessor.  ...  In addition, the break-even threshold interval for amortizing the shutdown overhead is considered. By evaluating each set of stretched task computations, an energy-efficient set is obtained.  ...  CONCLUSION This paper proposes an algorithm to minimize the total energy consumption of an application being executed on an on-chip multiprocessor.  ... 
doi:10.1109/tcad.2008.2006094 fatcat:tctvzjuxsndtlmasnhpo5ebwxa

Energy-efficient fault tolerance in chip multiprocessors using Critical Value Forwarding

Pramod Subramanyan, Virendra Singh, Kewal K. Saluja, Erik Larsson
2010 2010 IEEE/IFIP International Conference on Dependable Systems & Networks (DSN)  
In this paper we introduce a new energy-efficient fault-tolerant CMP architecture known as Redundant Execution using Critical Value Forwarding (RECVF).  ...  Our evaluation shows that RECVF consumes 37% less energy than conventional dual modular redundant (DMR) execution of a program.  ...  This work is partially supported by the Swedish Foundation for International Cooperation in Research and Higher Education through an institutional grant for younger researchers and by the National Science  ... 
doi:10.1109/dsn.2010.5544918 dblp:conf/dsn/SubramanyanSSL10 fatcat:7n7tkv6jvzb77f7kwzgrtpq6ve

High-Performance Energy-Efficient Multicore Embedded Computing

A. Munir, S. Ranka, A. Gordon-Ross
2012 IEEE Transactions on Parallel and Distributed Systems  
high-performance embedded computing demands in an energy-efficient manner.  ...  This paper outlines typical requirements of embedded applications and discusses state-of-the-art hardware/software high-performance energy-efficient embedded computing (HPEEC) techniques that help meeting  ...  Power profiling is important for energy-efficient HPEEC system design.  ... 
doi:10.1109/tpds.2011.214 fatcat:vagqmojdsjevvc2u2ewqrcjjpq

An adaptive chip-multiprocessor architecture for future mobile terminals

Mladen Nikitovic, Mats Brorsson
2002 Proceedings of the international conference on Compilers, architecture, and synthesis for embedded systems - CASES '02  
With several processors on one chip we can build a chip-multiprocessor (CMP) that can easily scale performance efficiently.  ...  We propose an adaptive chip-multiprocessor (CMP) architecture, where the number of active processors is dynamically adjusted to the current workload need in order to save energy while preserving performance  ...  ACKNOWLEDGMENTS The research in this paper is partly supported by the Swedish Foundation for Strategic Research in the INTELECT programme.  ... 
doi:10.1145/581636.581638 fatcat:pplg744ocnhtvizu32iab6jgp4

An adaptive chip-multiprocessor architecture for future mobile terminals

Mladen Nikitovic, Mats Brorsson
2002 Proceedings of the international conference on Compilers, architecture, and synthesis for embedded systems - CASES '02  
With several processors on one chip we can build a chip-multiprocessor (CMP) that can easily scale performance efficiently.  ...  We propose an adaptive chip-multiprocessor (CMP) architecture, where the number of active processors is dynamically adjusted to the current workload need in order to save energy while preserving performance  ...  ACKNOWLEDGMENTS The research in this paper is partly supported by the Swedish Foundation for Strategic Research in the INTELECT programme.  ... 
doi:10.1145/581630.581638 dblp:conf/cases/NikitovicB02 fatcat:3ss63yhaezb5hl5xbswruld4pm

A Hardware-Software Collaborated Method for Soft-Error Tolerant MPSoC

Weichen Liu, Jiang Xu, Xuan Wang, Yu Wang, Wei Zhang, Yaoyao Ye, Xiaowen Wu, Mahdi Nikdast, Zhehui Wang
2011 2011 IEEE Computer Society Annual Symposium on VLSI  
performance and energy efficiency and lower cost per function.  ...  Multiprocessor systems-on-chip (MPSoCs) are attractive platforms for embedded applications with growing complexity, because integrating a system or a complex subsystem on a single chip provides better  ...  applications, because integrating a system or a complex subsystem on a single chip provides better performance and energy efficiency and lower cost per function [1] .  ... 
doi:10.1109/isvlsi.2011.48 dblp:conf/isvlsi/LiuXWWZYWNW11 fatcat:kdxseofyejanbgfni5xavsm5bm
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