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Energy-efficient issue queue design
2003
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
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The out-of-order issue queue (IQ), used in modern superscalar processors is a considerable source of energy dissipation. ...
We consider design alternatives that result in significant reductions in the power dissipation of the IQ (by as much as 75%) through the use of comparators that dissipate energy mainly on a tag match, ...
The new comparator is 75% more energy-efficient on the average than the traditional comparator. ...
doi:10.1109/tvlsi.2003.814321
fatcat:ejlogejduzhx7kolaciem4iaqi
Energy efficient comparators for superscalar datapaths
2004
IEEE transactions on computers
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For the same delay, the proposed 8-bit comparators dissipate 70 percent less energy than the traditional designs if used within issue queues and 73 percent less energy if used within load-store queues. ...
We also find that the use of a hybrid 32-bit comparator, comprised of three traditional 8-bit blocks and one proposed 8-bit block, is the most energy-efficient solution for the use in the load-store queue ...
queue design and the design with the split issue queues is that the destination tags of the floating-point instructions are not broadcast across the integer issue queue. ...
doi:10.1109/tc.2004.29
fatcat:aq5vry3fyfebvd2u3npz7si4ay
A Multi-queue Approach of Energy Efficient Task Scheduling for Sensor Hubs
2020
Chinese journal of electronics
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Energy efficiency is one of the most important issues for sensor hubs. To attack this challenge, this paper proposes a task scheduling scheme for sensor hubs to improve their energy efficiency. ...
A multi-queue-based framework is designed, and its theoretical model and the corresponding mathematical analyses are presented. ...
[10] dealt with the energy efficiency problem from MAC layer, and designed an energy efficient MAC protocol for Linear WSN. ...
doi:10.1049/cje.2020.02.001
fatcat:qrdhvcdyvre4jfpebiigwnu2pe
Tag simplification: Achieving power efficiency through reducing the complexity of the wakeup logic
2011
2011 International Conference on Energy Aware Computing
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Our design reduces the dynamic energy dissipation of the CAM array inside the issue queue 15% with virtually no impact on performance. ...
Keywords-CAM logic; issue queue; wakeup logic; low-power 978-1-4673-0465-8/11/$26.00 ©2011 IEEE ...
for energy efficiency. ...
doi:10.1109/iceac.2011.6136701
dblp:conf/iceac/AykenarOBE11
fatcat:eqgkyqcqlbdphesjiyshubpm24
FIFOrder MicroArchitecture: Ready-Aware Instruction Scheduling for OoO Processors
2019
2019 Design, Automation & Test in Europe Conference & Exhibition (DATE)
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Our design, FIFOrder, is able to steer more than 60% of instructions to the cheaper FIFO queues, providing a 50% energy savings over a traditional out-of-order instruction queue design, while delivering ...
With such additional queues, we can reduce the size and width of the expensive out-of-order instruction queue, without reducing the processor's overall issue width and depth. ...
In our design instructions that are placed in the FIFO queues are issued directly from their respective queues, and do not need to pay the latency and energy cost of being re-inserted into the IQ. ...
doi:10.23919/date.2019.8715034
dblp:conf/date/Alipour0KB19
fatcat:saomqfdwxnhshder2lbyucf6ti
Power efficient comparators for long arguments in superscalar processors
2003
Proceedings of the 2003 international symposium on Low power electronics and design - ISLPED '03
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As an example of this general approach, we show how fast and energy-efficient comparators can be designed for comparing addresses within the load-store queue of a superscalar processor. ...
These designs, however, are limited to at most 8-bit long arguments. In this paper, we examine the designs of energy-efficient comparators capable of comparing arguments as long as 32 bits in size. ...
Such designs are significantly more energy-efficient than the traditional designs. In the case of the issue queue, only a few bits -no more than 8 -need to be compared. ...
doi:10.1145/871597.871601
fatcat:72zeb3frsrahnjetnt5z545aeu
Power efficient comparators for long arguments in superscalar processors
2003
Proceedings of the 2003 international symposium on Low power electronics and design - ISLPED '03
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As an example of this general approach, we show how fast and energy-efficient comparators can be designed for comparing addresses within the load-store queue of a superscalar processor. ...
These designs, however, are limited to at most 8-bit long arguments. In this paper, we examine the designs of energy-efficient comparators capable of comparing arguments as long as 32 bits in size. ...
Such designs are significantly more energy-efficient than the traditional designs. In the case of the issue queue, only a few bits -no more than 8 -need to be compared. ...
doi:10.1145/871506.871601
dblp:conf/islped/PonomarevKEG03
fatcat:waeskferevechbuq5e2mhmwyjq
SEED
2006
Proceedings of the 15th international conference on Parallel architectures and compilation techniques - PACT '06
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Compared to a conventional issue queue design, which is assumed favorably to scale in size without any impact on cycle time, the performance degradation of our design is 3% for both INT and FP suites of ...
We call this design "Scalable, Efficient Enforcement of Dependences (SEED)". We present a detailed design and analysis of SEED through an extensive evaluation. ...
Therefore, conventional designs in which energy efficiency is not a first-class design consideration will no longer be viable. ...
doi:10.1145/1152154.1152193
dblp:conf/IEEEpact/Mesa-MartinezHR06
fatcat:6j7xgjn7nzdwpdzynt7vu5ywne
S/DC: A storage and energy efficient data prefetcher
2012
2012 Design, Automation & Test in Europe Conference & Exhibition (DATE)
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Energy efficiency is becoming a major constraint in processor designs. Every component of the processor should be reconsidered to reduce wasted energy and area. ...
Prefetcher designs have important impact on the energy efficiency of the memory hierarchy. Stride prefetchers require little storage, but cannot handle irregular access patterns. ...
MOTIVATION To optimize a processor for energy efficiency, the design choice of each component should be reconsidered. ...
doi:10.1109/date.2012.6176515
dblp:conf/date/DangWTLYW12
fatcat:ehvqkjmsznhdrdvcf6rev55wpm
Energy efficient co-adaptive instruction fetch and issue
2003
Proceedings of the 30th annual international symposium on Computer architecture - ISCA '03
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While the former increases overall processor energy consumption, the latter aggravates the issue queue hot spot problem. ...
Compared to a conventional fetch gating scheme based on flow-rate matching, we demonstrate 20% better overall energy-delay with a 44% additional reduction in issue queue energy. ...
overall chip and issue queue energy savings. ...
doi:10.1145/859634.859636
fatcat:yzd6achg2ngflkf7kqvjbsuvya
Energy efficient co-adaptive instruction fetch and issue
2003
SIGARCH Computer Architecture News
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While the former increases overall processor energy consumption, the latter aggravates the issue queue hot spot problem. ...
Compared to a conventional fetch gating scheme based on flow-rate matching, we demonstrate 20% better overall energy-delay with a 44% additional reduction in issue queue energy. ...
overall chip and issue queue energy savings. ...
doi:10.1145/871656.859636
fatcat:dql62trvdbey5pnunoszxxnau4
Energy efficient co-adaptive instruction fetch and issue
2003
Proceedings of the 30th annual international symposium on Computer architecture - ISCA '03
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While the former increases overall processor energy consumption, the latter aggravates the issue queue hot spot problem. ...
Compared to a conventional fetch gating scheme based on flow-rate matching, we demonstrate 20% better overall energy-delay with a 44% additional reduction in issue queue energy. ...
overall chip and issue queue energy savings. ...
doi:10.1145/859618.859636
fatcat:m6hmoovaqzdtlegmprusk5k674
A Power-Efficient and Scalable Load-Store Queue Design
[chapter]
2005
Lecture Notes in Computer Science
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In this paper we propose an efficient load-store queue state filtering mechanism that provides a significant energy reduction (on average 35% in the LSQ and 3.5% in the whole processor), and only incurs ...
The load-store queue (LQ-SQ) of modern superscalar processors is responsible for keeping the order of memory operations. ...
In this paper, we propose a more efficient LSQ design that allows for a more efficient energy usage. ...
doi:10.1007/11556930_1
fatcat:vad5cc4sgfhkxj4mfzjkf3lrze
A Gradient-Assisted Energy-Efficient Backpressure Scheduling Algorithm for Wireless Sensor Networks
2015
International Journal of Distributed Sensor Networks
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In this paper, we focus on studying the design of energy efficient backpressure based algorithm. ...
For this purpose, we propose a gradient-assisted energy-efficient backpressure scheduling algorithm (GRAPE) for WSNs. ...
Energy use efficiency is a big issue for backpressure based algorithm to be used in a WSN. ...
doi:10.1155/2015/460506
fatcat:72t5ktvkdrhrbc6dsnk536hp3e
Red Congestion Control with Energy Aware Auction Based Route Selection in MANET
2020
International journal of recent technology and engineering
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It increasing buffer space of the queue and it reduce the packet loss and control transmission delay. ...
Congestion is a very big issue in mobile ad hoc network. In MANET has various congestion control algorithm to solve this issue. RED algorithm is the one of the congestion control algorithm. ...
The economist design a set of rules and instructions. It gives a very efficient and trustable auction methods. ...
doi:10.35940/ijrte.e5933.018520
fatcat:om3ulyfvuvb5pn7skufvnbbure
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