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Energy-conscious compilation based on voltage scaling

H. Saputra, M. Kandemir, N. Vijaykrishnan, M. J. Irwin, J. S. Hu, C-H. Hsu, U. Kremer
2002 Proceedings of the joint conference on Languages, compilers and tools for embedded systems software and compilers for embedded systems - LCTES/SCOPES '02  
In this paper, we present t wo compiler-directed energy optimization strategies based on voltage scaling: static voltage scaling and dynamic voltage scaling.  ...  Our compilation strategy is based on integer linear programming and can accommodate energy performance constraints.  ...  STATIC VOLTAGE SCALING In this section, we present a compiler-directed energy optimization strategy based on voltage scaling.  ... 
doi:10.1145/513830.513832 fatcat:jboafsidijcdjdnpgmejuu77pa

Energy-conscious compilation based on voltage scaling

H. Saputra, M. Kandemir, N. Vijaykrishnan, M. J. Irwin, J. S. Hu, C-H. Hsu, U. Kremer
2002 Proceedings of the joint conference on Languages, compilers and tools for embedded systems software and compilers for embedded systems - LCTES/SCOPES '02  
In this paper, we present t wo compiler-directed energy optimization strategies based on voltage scaling: static voltage scaling and dynamic voltage scaling.  ...  Our compilation strategy is based on integer linear programming and can accommodate energy performance constraints.  ...  STATIC VOLTAGE SCALING In this section, we present a compiler-directed energy optimization strategy based on voltage scaling.  ... 
doi:10.1145/513829.513832 dblp:conf/lctrts/SaputraKVIHHK02 fatcat:ms7muectczcopapc4x6rcm6gqa

Energy-conscious compilation based on voltage scaling

H. Saputra, M. Kandemir, N. Vijaykrishnan, M. J. Irwin, J. S. Hu, C-H. Hsu, U. Kremer
2002 SIGPLAN notices  
In this paper, we present t wo compiler-directed energy optimization strategies based on voltage scaling: static voltage scaling and dynamic voltage scaling.  ...  Our compilation strategy is based on integer linear programming and can accommodate energy performance constraints.  ...  STATIC VOLTAGE SCALING In this section, we present a compiler-directed energy optimization strategy based on voltage scaling.  ... 
doi:10.1145/566225.513832 fatcat:zcmdisnirnazndy3hwainplode

DVFS-Aware Consolidation for Energy-Efficient Clouds

Patricia Arroba, Jose M. Moya, Jose L. Ayala, Rajkumar Buyya
2015 2015 International Conference on Parallel Architecture and Compilation (PACT)  
Also, workload variation impacts on the performance of two of the main strategies for energy-efficiency in Cloud data centers: Dynamic Voltage and Frequency Scaling (DVFS) and Consolidation.  ...  Cloud Computing; Dynamic Voltage and Frequency Scaling; Dynamic Consolidation; Energy Efficiency I.  ...  The proposed algorithm is based on a bin packing problem [1] where servers are represented as bins with variable sizes due to the frequency scaling.  ... 
doi:10.1109/pact.2015.59 dblp:conf/IEEEpact/ArrobaMAB15 fatcat:psxolpq5lbei7cqzlg2l6rgsiy

An intra-task dynamic voltage scaling method for SoC design with hierarchical FSM and synchronous dataflow model

Sunghyun Lee, Kiyoung Choi, Sungjoo Yoo
2002 Proceedings of the 2002 international symposium on Low power electronics and design - ISLPED '02  
In general programs, since determining exact execution paths in compile time or runtime is not possible, existing methods assume worst/average-case execution paths and take static voltage scaling approaches  ...  The exact workload enables to calculate optimal voltage level which gives optimal energy consumption while satisfying the given timing constraint.  ...  For such a power-conscious design, recently, significant research efforts have been made on dynamic voltage scaling (DVS) exploiting the quadratic scale of energy consumption to the power supply voltage  ... 
doi:10.1145/566427.566432 fatcat:63blvcnqt5fbzeglbzpkftqnfm

An intra-task dynamic voltage scaling method for SoC design with hierarchical FSM and synchronous dataflow model

Sunghyun Lee, Sungjoo Yoo, Kiyoung Choi
2002 Proceedings of the International Symposium on Low Power Electronics and Design  
In general programs, since determining exact execution paths in compile time or runtime is not possible, existing methods assume worst/average-case execution paths and take static voltage scaling approaches  ...  The exact workload enables to calculate optimal voltage level which gives optimal energy consumption while satisfying the given timing constraint.  ...  For such a power-conscious design, recently, significant research efforts have been made on dynamic voltage scaling (DVS) exploiting the quadratic scale of energy consumption to the power supply voltage  ... 
doi:10.1109/lpe.2002.146716 fatcat:hjmssunfajca5dd3xyhgbx4wca

An intra-task dynamic voltage scaling method for SoC design with hierarchical FSM and synchronous dataflow model

Sunghyun Lee, Kiyoung Choi, Sungjoo Yoo
2002 Proceedings of the 2002 international symposium on Low power electronics and design - ISLPED '02  
In general programs, since determining exact execution paths in compile time or runtime is not possible, existing methods assume worst/average-case execution paths and take static voltage scaling approaches  ...  The exact workload enables to calculate optimal voltage level which gives optimal energy consumption while satisfying the given timing constraint.  ...  For such a power-conscious design, recently, significant research efforts have been made on dynamic voltage scaling (DVS) exploiting the quadratic scale of energy consumption to the power supply voltage  ... 
doi:10.1145/566408.566432 dblp:conf/islped/LeeCY02 fatcat:4gdtviizubbi3nj5fqsckvhdr4

Parallel Architecture Core (PAC)—the First Multicore Application Processor SoC in Taiwan Part I: Hardware Architecture & Software Development Tools

David Chih-Wei Chang, Tay-Jyi Lin, Chung-Ju Wu, Jenq-Kuen Lee, Yuan-Hua Chu, An-Yeu Wu
2010 Journal of Signal Processing Systems  
The first part of the two introductory papers of PAC describes the hardware architecture of the PACDSP core, its software development tools, and the PAC SoC with dynamic voltage and frequency scaling (  ...  energy efficiency for multimedia processing such as the real-time H.264 codec.  ...  A dual-core PAC SoC, which is composed of a PACDSP core, an ARM9 core and various on-chip peripherals, has been designed with dynamic voltage and frequency scaling (DVFS) capability.  ... 
doi:10.1007/s11265-010-0470-0 fatcat:3bzqwdxku5aphc5pqmf5iffmya

Instruction level and operating system profiling for energy exposed software

A. Sinha, N. Ickes, A.P. Chandrakasan
2003 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
The technique is shown to have an estimation error of less than 3% with trivial runtime overhead, based on a set of application programs evaluated on the StrongARM SA-1100 and Hitachi SH-4 microprocessors  ...  Energy conscious software design can significantly improve the energy efficiency of a portable system. A software energy estimation technique using instruction class profiling is presented.  ...  When the operating frequency is fixed and the supply voltage is scaled, the energy scales almost quadratically.  ... 
doi:10.1109/tvlsi.2003.819569 fatcat:ohpnaazluzb4naxm6hd6oyt2xm

Power Analysis and Optimization Techniques for Energy Efficient Computer Systems [chapter]

Wissam Chedid, Chansu Yu, Ben Lee
2005 Advances in Computers  
On the other hand, dynamic power management techniques are applied during run-time, and are used to monitor system workload and adapt the system's behavior dynamically to save energy.  ...  Mechanisms in the first category use analytical energy models that are integrated into existing simulators to measure the system's power consumption and thus help engineers to test power-conscious hardware  ...  Among many possibilities, it focuses on combining dynamic register file reconfiguration with voltage/frequency scaling.  ... 
doi:10.1016/s0065-2458(04)63004-x fatcat:qqgqxgtgerh3dikj3khtzmysqe

System-level power-aware design techniques in real-time systems

O.S. Unsal, I. Koren
2003 Proceedings of the IEEE  
We start with the motivation for focusing on these systems and provide a brief discussion on power and energy objectives. We then follow with a survey of current research on a layer by layer basis.  ...  architectural, compiler, operating system and networking layers.  ...  bus, cache region reservation, voltage and frequency scaling, battery-consciousness, Field Programmable Gate Arrays (FPGA), and task movement.  ... 
doi:10.1109/jproc.2003.814617 fatcat:jdhfjwawuvetrjngqhliysufwq

Designing low-power circuits: practical recipes

L. Benini, G. De Micheli, E. Macii
2001 IEEE Circuits and Systems Magazine  
We will focus solely on digital circuits, and we will restrict our attention to CMOS devices, this technology being the most widely adopted in current VLSI systems.  ...  In other words, our contribution should not be intended as an exhaustive survey of the existing literature on low-power design; rather, we would like to provide insights a designer can rely upon when power  ...  The techniques based on voltage scaling described above require significant process and system support, which imply additional costs that can be justified only for largevolume applications.  ... 
doi:10.1109/7384.928306 fatcat:xm5slwbg5jekpg3pg3mzqruc7e

Towards Energy Aware Scheduling for Precedence Constrained Parallel Tasks in a Cluster with DVFS

Lizhe Wang, Gregor von Laszewski, Jay Dayal, Fugang Wang
2010 2010 10th IEEE/ACM International Conference on Cluster, Cloud and Grid Computing  
This paper aims to develop scheduling heuristics and to present application experience for reducing power consumption of parallel tasks in a cluster with the Dynamic Voltage Frequency Scaling (DVFS) technique  ...  By increasing task execution time within an affordable limit, this paper develops scheduling heuristics to reduce energy consumption of a tasks execution and discusses the relationship between energy consumption  ...  [30] proposes an energy-conscious scheduling (ECS) heuristic for parallel tasks on heterogeneous computing systems.  ... 
doi:10.1109/ccgrid.2010.19 dblp:conf/ccgrid/WangLDW10 fatcat:kiu5oibsjjaphedihykmeeuiwa

Parallel Evolutionary Algorithms for Energy Aware Scheduling [chapter]

Yacine Kessaci, Mohand Mezmaz, Nouredine Melab, El-Ghazali Talbi, Daniel Tuyttens
2011 Studies in Computational Intelligence  
In computing systems, minimizing energy consumption can significantly reduces the amount of energy bills. The demand for computing systems steadily increases and the cost of energy continues to rise.  ...  In embedded systems, reducing the use of energy allows to extend the autonomy of these systems. In addition, the reduction of energy decreases greenhouse gas emissions.  ...  The energy saving of our approach exploits the dynamic voltage scaling (DVS).  ... 
doi:10.1007/978-3-642-21271-0_4 fatcat:sejk7d5dnrefzmmcji4zzm5xgy

Type Systems in Resource-Aware Programming: Opportunities and Challenges [article]

Alcides Fonseca, Guilherme Espada
2022 arXiv   pre-print
On the other hand, understanding the time and energy consumption of the execution of a program requires manual testing.  ...  In this paper, we identify existing work on using type systems for energy awareness, and define the requirements for a practical approach, which the existing approaches do not address fully.  ...  Experimental evaluation was conducted on hardware provided by projects CMU-Portugal CAMELOT (LISBOA-01-0247-FEDER-045915) and Resource-Aware Programming (EXPL/CCI-COM/1306/2021) .  ... 
arXiv:2205.15211v2 fatcat:qvy4ypxvjzcgpexikjmbozxlea
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