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Energy-efficient processor design using multiple clock domains with dynamic voltage and frequency scaling

G. Semeraro, G. Magklis, R. Balasubramonian, D.H. Albonesi, S. Dwarkadas, M.L. Scott
Proceedings Eighth International Symposium on High Performance Computer Architecture  
a single clock and voltage system. der to allow a single system to accommodate processors of different frequencies.  ...  Using applications from the MediaBench, Olden, and SPEC2000 benchmark suites, we obtain an average energy-delay product improvement of 20% with MCD compared to a modest 3% savings from voltage scaling  ...  The baseline MCD design, which simply uses multiple clock domains with no voltage or frequency scaling, shows an average performance degradation of less than 4%, with average energy cost of 1.5%.  ... 
doi:10.1109/hpca.2002.995696 dblp:conf/hpca/SemeraroMBADS02 fatcat:opapjsictvhrlbwdxnynedewxi

Power efficiency of voltage scaling in multiple clock, multiple voltage cores

Anoop Iyer, Diana Marculescu
2002 Computer-Aided Design (ICCAD), IEEE International Conference on  
By exploiting the flexibility of independent dynamic voltage scaling the various clock domains, the power efficiency of GALS designs can be improved by 12% on average, and up to 20% more in select cases  ...  Using this design exploration environment we were able to assess the power/performance tradeoffs available for Multiple Clock, Single Voltage (MCSV), as well as Multiple Clock, Dynamic Voltage (MCDV) cores  ...  Theoretical Efficiency of Voltage Scaling in MCDV Cores In this section, we provide some theoretical results on the efficiency of using fine-grained dynamic voltage scaling in multiple-clock dynamic voltage  ... 
doi:10.1145/774572.774629 dblp:conf/iccad/IyerM02 fatcat:st2sjbppozghpgoxmqlxf6zu2y

Toward a multiple clock/voltage island design style for power-aware processors

E. Talpes, D. Marculescu
2005 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
As a solution to this problem, designers have recently suggested the use of frequency islands that are locally clocked and externally communicate with each other using mixed clock communication schemes  ...  Such a design style fits nicely with the recently proposed concept of voltage islands that, in addition, can potentially enable fine-grain dynamic power management by simultaneous voltage and frequency  ...  To this end, we provide some theoretical results on the efficiency of using fine-grained dynamic voltage scaling in multiple-clock dynamic voltage cores.  ... 
doi:10.1109/tvlsi.2005.844305 fatcat:7azarbcc4rbzfbimlassepc5ki

A critical analysis of application-adaptive multiple clock processors

Emil Talpes, Diana Marculescu
2003 Proceedings of the 2003 international symposium on Low power electronics and design - ISLPED '03  
While performance is worse than in the fully synchronous case (with an average of 10%), the paper identifies the ability of the GALS processor to use different clock frequencies and supply voltages for  ...  The same idea of scaling the clock frequency and the supply voltage is studied in [8] , concluding that such  ...  Energy reduction for a GALS design using different asynchronous communication mechanisms One advantage of the GALS architectures is the ability to scale the voltage and clock speed independently, for each  ... 
doi:10.1145/871506.871576 dblp:conf/islped/TalpesM03 fatcat:erneynlrpveqpnjlzksfuppbba

A critical analysis of application-adaptive multiple clock processors

Emil Talpes, Diana Marculescu
2003 Proceedings of the 2003 international symposium on Low power electronics and design - ISLPED '03  
While performance is worse than in the fully synchronous case (with an average of 10%), the paper identifies the ability of the GALS processor to use different clock frequencies and supply voltages for  ...  The same idea of scaling the clock frequency and the supply voltage is studied in [8] , concluding that such  ...  Energy reduction for a GALS design using different asynchronous communication mechanisms One advantage of the GALS architectures is the ability to scale the voltage and clock speed independently, for each  ... 
doi:10.1145/871575.871576 fatcat:gl75c2v2u5fqrp2bqafmy76o5i

High Performance, Energy Efficiency, and Scalability With GALS Chip Multiprocessors

Zhiyi Yu, B.M. Baas
2009 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
The GALS methodology simplifies clock tree design, provides opportunities to use clock and voltage scaling jointly in system submodules to achieve high energy efficiencies, and can also result in easily  ...  savings of approximately 25% using dynamic clock and voltage scaling for many general purpose applications.  ...  Mohsenin, and other VCL colleagues; R. Krishnamurthy, M. Anders, S. Mathew, and Y. P. Cheng.  ... 
doi:10.1109/tvlsi.2008.2001947 fatcat:zrlhdhuagfh4bh25iwr7q6kwqa

A comparative study of voltage/frequency scaling in NoC

Saeeda Usman, Samee U. Khan, Sikandar Khan
2013 IEEE International Conference on Electro-Information Technology , EIT 2013  
Voltage and frequency is dynamically scaled to produce energy efficient multi-core networkon-chip (NoC).  ...  We also highlight the most promising high performance and energy minimizing techniques. Index Terms-Network-on-chip, dynamic voltage and frequency scaling, leakage power  ...  ACKNOWLEDGMENTS The authors are grateful to Muhammad Awais, Osman Khalid, and Assad Abbas for their valuable suggestions.  ... 
doi:10.1109/eit.2013.6632716 dblp:conf/eit/UsmanKK13 fatcat:o6pxc4vvnjenboa7ljblpnr3ia

Energy Efficient Multi-Core Processing

Charles Leech, Tom J. Kazmierski
2014 Electronics  
concept of minimal architecture synthesis and how it can be used to produce an application specific, energy efficient processor.  ...  This paper evaluates the present state of the art of energy-efficient embedded processor design techniques and demonstrates, how small, variable-architecture embedded processors may exploit a run-time  ...  ACKNOWLEDGMENT This work was supported by the Engineering and Physical Sciences Research Council (EPSRC), UK under grant number EP/K034448/1 " PRiME: Power-efficient, Reliable, Many-core Embedded systems  ... 
doi:10.7251/els1418003l fatcat:ehztmbwggvayddswnnp6qxg2ra

System level analysis of fast, per-core DVFS using on-chip switching regulators

Wonyoung Kim, Meeta S. Gupta, Gu-Yeon Wei, David Brooks
2008 High-Performance Computer Architecture  
Dynamic voltage and frequency scaling (DVFS) is a well-known technique to reduce energy in digital systems, but the effectiveness of DVFS is hampered by slow voltage transitions that occur on the order  ...  Voltage regulators that are integrated onto the same chip as the microprocessor core provide the benefit of both nanosecond-scale voltage switching and per-core voltage control.  ...  Acknowledgments This work is supported by National Science Foundation grants CCF-0429782 and CSR-0720566 and Army Research Office grant W911NF-07-0331 (DARPA YFA).  ... 
doi:10.1109/hpca.2008.4658633 dblp:conf/hpca/KimGWB08 fatcat:r3osegzwubdfvclqjrzfrafwqy

Formal online methods for voltage/frequency control in multiple clock domain microprocessors

Qiang Wu, Philo Juang, Margaret Martonosi, Douglas W. Clark
2004 ACM SIGOPS Operating Systems Review  
Dynamic Voltage and Frequency Scaling (DVFS) in an MCD processor has the extra flexibility to adjust the voltage and frequency in each domain independently.  ...  Multiple Clock Domain (MCD) processors are a promising future alternative to today's fully synchronous designs.  ...  We also thank Greg Semeraro, Yongkang Zhu, and Diana Marculescu for their helpful discussions during the development of this work; and Youfeng Wu and the anonymous reviewers for their useful comments and  ... 
doi:10.1145/1037949.1024423 fatcat:kjvaxzwv4fbgdgevtawq5aboju

Formal online methods for voltage/frequency control in multiple clock domain microprocessors

Qiang Wu, Philo Juang, Margaret Martonosi, Douglas W. Clark
2004 Proceedings of the 11th international conference on Architectural support for programming languages and operating systems - ASPLOS-XI  
Dynamic Voltage and Frequency Scaling (DVFS) in an MCD processor has the extra flexibility to adjust the voltage and frequency in each domain independently.  ...  Multiple Clock Domain (MCD) processors are a promising future alternative to today's fully synchronous designs.  ...  We also thank Greg Semeraro, Yongkang Zhu, and Diana Marculescu for their helpful discussions during the development of this work; and Youfeng Wu and the anonymous reviewers for their useful comments and  ... 
doi:10.1145/1024393.1024423 dblp:conf/asplos/WuJMC04 fatcat:mb7uqr5pz5gm3gl3ysz6c2nkza

Formal online methods for voltage/frequency control in multiple clock domain microprocessors

Qiang Wu, Philo Juang, Margaret Martonosi, Douglas W. Clark
2004 SIGARCH Computer Architecture News  
Dynamic Voltage and Frequency Scaling (DVFS) in an MCD processor has the extra flexibility to adjust the voltage and frequency in each domain independently.  ...  Multiple Clock Domain (MCD) processors are a promising future alternative to today's fully synchronous designs.  ...  We also thank Greg Semeraro, Yongkang Zhu, and Diana Marculescu for their helpful discussions during the development of this work; and Youfeng Wu and the anonymous reviewers for their useful comments and  ... 
doi:10.1145/1037947.1024423 fatcat:2brganjj2bfqhky53qdvzsrqm4

Formal online methods for voltage/frequency control in multiple clock domain microprocessors

Qiang Wu, Philo Juang, Margaret Martonosi, Douglas W. Clark
2004 SIGPLAN notices  
Dynamic Voltage and Frequency Scaling (DVFS) in an MCD processor has the extra flexibility to adjust the voltage and frequency in each domain independently.  ...  Multiple Clock Domain (MCD) processors are a promising future alternative to today's fully synchronous designs.  ...  We also thank Greg Semeraro, Yongkang Zhu, and Diana Marculescu for their helpful discussions during the development of this work; and Youfeng Wu and the anonymous reviewers for their useful comments and  ... 
doi:10.1145/1037187.1024423 fatcat:wfcbwh7moff2ddjoljjt3fa7xm

Dynamic frequency and voltage scaling for a multiple-clock-domain microprocessor

G. Magklis, G. Semeraro, D.H. Albonesi, S.G. Dropsho, S. Dwarkadas, M.L. Scott
2003 IEEE Micro  
Moreover, domains can have independent voltage and frequency control, enabling dynamic voltage scaling at the domain level.  ...  A multiple clock domain (MCD) microarchitecture, 1 which uses a globally asynchronous, locally synchronous (GALS) clocking style, 2,3 permits future aggressive frequency increases, maintains a synchronous  ...  Moreover, domains can have independent voltage and frequency control, enabling dynamic voltage scaling at the domain level.  ... 
doi:10.1109/mm.2003.1261388 fatcat:jyo6bovg4ne6hdqqe7v4xdu3du

Cooperative multithreading on embedded multiprocessor architectures enables energy-scalable design

P. Schaumont, Bo-Cheng Charles Lai, Wei Qin, I. Verbauwhede
2005 Proceedings. 42nd Design Automation Conference, 2005.  
The savings are obtained by voltage-and frequency-scaling of the individual processors.  ...  The energy-scaled quadprocessor version results in a 77 % energy reduction over the single-processor non-scaled implementation, at only a 2.2 % degradation in cycle count.  ...  A V/f-scaled multiprocessor has multiple clock frequencies.  ... 
doi:10.1109/dac.2005.193767 fatcat:ysdbhce73zadnpjqv5vyrbxo34
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