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Energy efficient mapping on manycore with dynamic and partial reconfiguration: Application to a smart camera

Robin Bonamy, Sébastien Bilavarn, Fabrice Muller, François Duhem, Simon Heywood, Philippe Millet, Fabrice Lemonnier
2018 International journal of circuit theory and applications  
Energy efficient mapping on manycore with dynamic and partial reconfiguration: Application to a smart camera.  ...  This paper describes a methodology to improve the energy efficiency of high-performance multiprocessor architectures with Dynamic and Partial Reconfiguration (DPR), based on a thorough application study  ...  ACKNOWLEDGMENTS This work was carried out under the BENEFIC project (CA505), a project labeled within the framework of CATRENE, the EUREKA cluster for Application and Technology Research in Europe on NanoElectronics  ... 
doi:10.1002/cta.2508 fatcat:edswp7sf3bh5pmzwtc5pvq2pqy

The Paramountcy of Reconfigurable Computing [chapter]

Reiner Hartenstein
2012 Energy-Efficient Distributed Computing Systems  
This chapter shows that Reconfigurable Computing is the silver bullet to obtain massively better energy efficiency as well as much better performance, also by the upcoming methodology of HPRC (high performance  ...  This paper introduces a new world model. 2 (section 19.6) is needed for simultaneously developing the scene toward parallel programming for manycore architectures and to structural programming for reconfigurable  ...  for partial/dynamic reconfiguration as well as ease of fabrication with standard CMOS processes.  ... 
doi:10.1002/9781118342015.ch18 fatcat:shfb4oycu5hu5boizx6oltlgwa

Towards future adaptive multiprocessor systems-on-chip: An innovative approach for flexible architectures

Fabrice Lemonnier, Philippe Millet, Gabriel Marchesan Almeida, Michael Hubner, Jurgen Becker, Sebastien Pillement, Olivier Sentieys, Martijn Koedam, Shubhendu Sinha, Kees Goossens, Christian Piguet, Marc-Nicolas Morgan (+1 others)
2012 2012 International Conference on Embedded Computer Systems (SAMOS)  
The upcoming generation of applications include smart cameras, drones, and cognitive radio.  ...  The different components are based on low power DSP cores and an eFPGA on which dedicated IPs can be dynamically configured at run-time.  ...  The upcoming generation of applications include smart cameras, drones, and cognitive radio.  ... 
doi:10.1109/samos.2012.6404179 dblp:conf/samos/LemonnierMAHBPSKSGPML12 fatcat:vvdjjie7xzaarjn44536hcx6ny

The TaPaSCo Open-Source Toolflow

Carsten Heinz, Jaco Hofmann, Jens Korinth, Lukas Sommer, Lukas Weber, Andreas Koch
2021 Journal of Signal Processing Systems  
as implementation platforms for efficient, application-specific accelerators for domains such as signal processing, machine learning and intelligent storage.  ...  many-core architectures from custom processing elements, and a simple, uniform programming interface to utilize spatially distributed, parallel computation on FPGAs.  ...  . to energy efficiency, performance, and area consumption.  ... 
doi:10.1007/s11265-021-01640-8 fatcat:t5y5t5vmp5ff3h635cx3y7to6e

2021 Index IEEE Transactions on Parallel and Distributed Systems Vol. 32

2022 IEEE Transactions on Parallel and Distributed Systems  
., +, TPDS July 2021 1866-1877 Improving HW/SW Adaptability for Accelerating CNNs on FPGAs Through A Dynamic/Static Co-Reconfiguration Approach.  ...  ., +, TPDS July 2021 1740-1752 Improving HW/SW Adaptability for Accelerating CNNs on FPGAs Through A Dynamic/Static Co-Reconfiguration Approach.  ...  Graph coloring Feluca: A Two-Stage Graph Coloring Algorithm With Color-Centric Paradigm on GPU. Zheng, Z., +,  ... 
doi:10.1109/tpds.2021.3107121 fatcat:e7bh2xssazdrjcpgn64mqh4hb4

Compiling Scilab to high performance embedded multicore systems

Timo Stripf, Oliver Oey, Thomas Bruckschloegl, Juergen Becker, Gerard Rauwerda, Kim Sunesen, George Goulas, Panayiotis Alefragis, Nikolaos S. Voros, Steven Derrien, Olivier Sentieys, Nikolaos Kavvadias (+5 others)
2013 Microprocessors and microsystems  
a Scilab-based toolchain which enables the efficient mapping of applications on multiprocessor platforms from a high level of abstraction.  ...  The mapping process of high performance embedded applications to today's multiprocessor system-onchip devices suffers from a complex toolchain and programming process.  ...  For mapping his algorithm to the target architecture, the end user wants a one-button solution that provides a high performance and energy efficient result.  ... 
doi:10.1016/j.micpro.2013.07.004 fatcat:pdh6kpwp25galdrdtvpv45l2cy

On the Confidence in Bit-Alias Measurement of Physical Unclonable Functions

Florian Wilde, Michael Pehl
2019 2019 17th IEEE International New Circuits and Systems Conference (NEWCAS)  
It further proposes a statistical hypothesis test to verify if a PUF design meets given specifications on Bit-Alias or bit-wise entropy.  ...  Application to several published PUF designs demonstrates the methods' capabilities. The results prove the need for a high number of samples when the unpredictability of PUFs is tested.  ...  However, in applications, in which energy-efficiency or cost is one of the key concerns, the use of traditional beamforming systems is limited.  ... 
doi:10.1109/newcas44328.2019.8961298 dblp:conf/newcas/WildeP19 fatcat:wv67uzuqlvcmhma3nahzdrr2ta

Technical Program

2022 2022 IEEE International Conference on Consumer Electronics (ICCE)  
The paper proposes a high dynamic range (HDR) tone mastering system which dynamically corrects the picture quality based on creative intent metadata to preserve content providers' creative intent in different  ...  Multiple sections of tone mapping curves with multiple adjustment points along explicit Bezier curve is modified for better tone mapping curve control.  ...  10:07 3D LiDAR Automatic Driving Environment Detection System Based on  ... 
doi:10.1109/icce53296.2022.9730380 fatcat:csqu3xqbczgdhpp3hbmvjpt26a

Hardware and Software Optimizations for Accelerating Deep Neural Networks: Survey of Current Trends, Challenges, and the Road Ahead

Maurizio Capra, Beatrice Bussolino, Alberto Marchisio, Guido Masera, Maurizio Martina, Muhammad Shafique
2020 IEEE Access  
In a scenario where several sophisticated algorithms need to be executed with limited energy and low latency, the need for cost-effective hardware platforms capable of implementing energy-efficient DL  ...  In addition to hardware solutions, this paper discusses some of the important security issues that these DNN and SNN models may have during their execution, and offers a comprehensive section on benchmarking  ...  models, recently the reconfigurable accelerators that allow to efficiently map different types of layers on the same hardware have gained importance.  ... 
doi:10.1109/access.2020.3039858 fatcat:nticzqgrznftrcji4krhyjxudu

Reconfigurable Antenna Systems: Platform implementation and low-power matters [article]

The authors would like also to acknowledge the invaluable help of CLEAR elettronica srl, which provide the control board for the scheduling and power management and SOLBIAN energie alternative srl, which  ...  Finally we are grateful to ENEA for the logistic and the support during the campaign.  ...  Fig. 6 6 OPERA Cyber-Physical System architecture: an ultra-low power manycore processor with acceleration function for CNNs is directly attached to the camera sensor and to the reconfigurable communication  ... 
doi:10.6092/polito/porto/2696507 fatcat:fah7dx2mareaxdboti7cobdh2y

2022 Roadmap on Neuromorphic Computing and Engineering [article]

Dennis V. Christensen, Regina Dittmann, Bernabé Linares-Barranco, Abu Sebastian, Manuel Le Gallo, Andrea Redaelli, Stefan Slesazeck, Thomas Mikolajick, Sabina Spiga, Stephan Menzel, Ilia Valov, Gianluca Milano (+47 others)
2022 arXiv   pre-print
The aim of this Roadmap is to present a snapshot of the present state of neuromorphic technology and provide an opinion on the challenges and opportunities that the future holds in the major areas of neuromorphic  ...  Modern computation based on the von Neumann architecture is today a mature cutting-edge science.  ...  Acknowledgements Roadmap on Neuromorphic Computing and Engineering This work was partially based on results obtained from a project, JPNP16007, commissioned by the New Energy and Industrial Technology  ... 
arXiv:2105.05956v3 fatcat:pqir5infojfpvdzdwgmwdhsdi4

Hardware/software co-design of global cloud system resolving models

Michael F. Wehner, Leonid Oliker, John Shalf, David Donofrio, Leroy A. Drummond, Ross Heikes, Shoaib Kamil, Celal Kono, Norman Miller, Hiroaki Miura, Marghoob Mohiyuddin, David Randall (+1 others)
2011 Journal of Advances in Modeling Earth Systems  
paths to realize the integration of such a model in the relatively near future.  ...  From this extrapolation, it is estimated that a credible kilometer scale atmospheric model would require a sustained computational rate of at least 28 Petaflop/s to provide scientifically useful climate  ...  to dynamics and so on.  ... 
doi:10.1029/2011ms000073 fatcat:dvf567ktnzcorlgzjk66ahwgsm

Eurolab-4-HPC Long-Term Vision on High-Performance Computing [article]

Theo Ungerer, Paul Carpenter
2018 arXiv   pre-print
The proposal on research topics is derived from the report and discussions within the road mapping expert group.  ...  , software, and applications in High-Performance Computing (HPC).  ...  NMC would be efficient in energy and space and applicable as embedded hardware accelerator in mobile systems.  ... 
arXiv:1807.04521v1 fatcat:5neetrgubjhnvcajcktpkohrzq

Memory and Information Processing in Neuromorphic Systems

Giacomo Indiveri, Shih-Chii Liu
2015 Proceedings of the IEEE  
more biological-like models of neurons and synapses together with a suite of adaptation and learning mechanisms analogous to the ones found in biological nervous systems.  ...  These architectures range from serial clocked implementations of multi-neuron systems to massively parallel asynchronous ones and from purely digital systems to mixed analog/digital systems which implement  ...  The flow-CPU works as a central control unit that can reconfigure the computing grid and the smart DMA at runtime.  ... 
doi:10.1109/jproc.2015.2444094 fatcat:enmuv4qr6bdktlh7t3rfwfj27i

Software challenges in extreme scale systems

Vivek Sarkar, William Harrod, Allan E Snavely
2009 Journal of Physics, Conference Series  
He also leads the UPC language effort, a consortium of industry and academic research institutions aiming to produce a unified approach to parallel C programming based on global address space methods.  ...  them, and scaling multiple chips to complete systems, for a range of real system applications, from highly scalable deep space exploration to trans-petaflops level supercomputing.  ...  Dynamic optimization strategies must be efficient enough to employ at run time, or must be used in conjunction with partial code generation and dynamic instantiation or a priori code generation and dynamic  ... 
doi:10.1088/1742-6596/180/1/012045 fatcat:iukutry2dvbitfdh6ng7kgz564
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