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Energy aware compilation for DSPs with SIMD instructions

Markus Lorenz, Lars Wehmeyer, Thorsten Dräger
2002 Proceedings of the joint conference on Languages, compilers and tools for embedded systems software and compilers for embedded systems - LCTES/SCOPES '02  
ENERGY AWARE CODE GENERATION Ù ØÓ Ø ÔÓÓÖ Ø Ò ÕÙ × ÓÖ Ò Ð Ò ÖÖ ÙÐ Ö ÔÖÓ ×¹ ×ÓÖ Ö Ø ØÙÖ ×¸Ø Ó Ò Ö Ø Ý ËÈ ÓÑÔ Ð Ö× × Ó Ø Ò Ò×ÙAE ÒØ Û Ø Ö ×Ô Ø ØÓ Ü ÙØ ÓÒ Ø Û Ø Ò Ø Ö Û Ö ÐÓÓÔ Ü × Ø ÐÐÓÛ × Þ Ð Ñ Øº ÁÒ Ø  ...  COMPILER FRAMEWORK Ò ÓÚ ÖÚ Û Ó Ø ÓÑÔ Ð Ø ÓÒ ÔÖÓ ×× Ò ÓÙÖ ÓÑÔ Ð Ö Ö Ñ ÛÓÖ × Ú Ò Ò ¬ ÙÖ ½º Ø ¬Ö×ظ ÖÓÒØ Ò ´ Ö Ä Ò ¾ ½ ¸½¿ µ Ö × Ú Ò ×ÓÙÖ ÔÖÓ Ö Ñ Ò ØÖ Ò×¹ ÓÖÑ× Ø ÒØÓ Ñ Ò Ò Ô Ò ÒØ ÒØ ÖÑ Ø Ö ÔÖ ¹ × ÒØ Ø ÓÒ´  ... 
doi:10.1145/513829.513847 dblp:conf/lctrts/LorenzWD02 fatcat:ln3y7xmz3baw5prmajglofjdgi

Code transformations and SIMD impact on embedded software energy/power consumption

Mostafa E. A. Ibrahim, Markus Rupp, Hossam A. H. Fahmy
2009 2009 International Conference on Computer Engineering & Systems  
Moreover, we evaluate the influence of employing Single Instruction Multiple Data (SIMD) on energy and power dissipation via the utilization of compiler intrinsic C-functions.  ...  The increasing demand for portable computing has elevated power consumption to be one of the most critical embedded systems design parameters.  ...  We study the effect of employing SIMD instructions with each of the compiler performance optimization levels (-o0 to -o3).  ... 
doi:10.1109/icces.2009.5383317 fatcat:36fj2wj3xjh2bovyjotg45jc7e

Efficient Utilization of SIMD Extensions

F. Franchetti, S. Kral, J. Lorenz, C.W. Ueberhuber
2005 Proceedings of the IEEE  
The work described includes (i) symbolic vectorization of DSP transforms, (ii) straight-line code vectorization for numerical kernels, and (iii) compiler backends for straight-line code with vector instructions  ...  This paper describes special purpose compiler technology that supports automatic performance tuning on machines with vector instructions.  ...  Special thanks go to Markus Pueschel and the SPIRAL team for years of fruitful cooperation. Important parts of the formal vectorization techniques were developed in cooperation with Markus Pueschel.  ... 
doi:10.1109/jproc.2004.840491 fatcat:4x6cjeyqlzfdjoau4et7rzoznm

Parallel Architecture Core (PAC)—the First Multicore Application Processor SoC in Taiwan Part I: Hardware Architecture & Software Development Tools

David Chih-Wei Chang, Tay-Jyi Lin, Chung-Ju Wu, Jenq-Kuen Lee, Yuan-Hua Chu, An-Yeu Wu
2010 Journal of Signal Processing Systems  
A complete toolchain with an optimizing C compiler has also been developed for PACDSP.  ...  AVLIW digital signal processor (PACDSP) has been developed from a proprietary instruction set with multimedia-rich instructions, a complexity-effective microarchitecture with an innovative distributed  ...  PACDSP features scalable datapath for easy adaptation to different applications, an innovative distributed & pingpong register organization, a rich & optimized instruction set with 8-bit/16-bit SIMD operations  ... 
doi:10.1007/s11265-010-0470-0 fatcat:3bzqwdxku5aphc5pqmf5iffmya

An innovative low-power high-performance programmable signal processor for digital communications

J. H. Moreno, V. Zyuban, U. Shvadron, F. D. Neeser, J. H. Derby, M. S. Ware, K. Kailas, A. Zaks, A. Geva, S. Ben-David, S. W. Asaad, T. W. Fox (+4 others)
2003 IBM Journal of Research and Development  
(SIMD) to achieve high-performance, its suitability as target for an optimizing high-level language compiler, and its explicit replacement of hardware resources by compile-time practices.  ...  Domains of application for next-generation DSPs can also be characterized by factors that are limiting with respect to their ability to satisfy application requirements.  ...  on different registers (SIMD) -Single instruction on subregisters (SIMD with packed data) -Multiple instructions on different registers (VLIW) -Multiple instructions on subregisters (VLIW and SIMD  ... 
doi:10.1147/rd.472.0299 fatcat:llzoroyazfawpdigtd7wts4usu

Overview of ITRI PAC project - from VLIW DSP processor to multicore computing platform

Tay-Jyi Lin, Chun-Nan Liu, Shau-Yin Tseng, Yuan-Hua Chu, An-Yeu Wu
2008 2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)  
This paper summarizes the technical contents of PACDSP, DVFS (dynamic voltage and frequency scaling) -enabled PAC SoC, and the energy-aware multimedia codec.  ...  In the first PAC project phase (2004~2006), a 5-way VLIW DSP (PACDSP) processor has been developed with our patented distributed & ping-pong register file and variable-length VLIW encoding techniques.  ...  In this paper, we have summarized the research and implementation results of a high-performance and low-power PACDSP core, a DVFS-enabled energy-aware PAC SoC with a PACDSP core and an ARM9 core, and energy-aware  ... 
doi:10.1109/vdat.2008.4542444 fatcat:7mwsalbtfjbwdi2ewccb7rejau

Enabling compiler flow for embedded VLIW DSP processors with distributed register files

Chung-Kai Chen, Ling-Hua Tseng, Shih-Chang Chen, Young-Jia Lin, Yi-Ping You, Chia-Han Lu, Jenq-Kuen Lee
2007 Proceedings of the 2007 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools - LCTES '07  
In this paper, we address the compiler optimization issues for PAC architecture, which is a 5-way issue DSP processor with distributed register files.  ...  We present an integrated flow to address several phases of compiler optimizations in interacting with distributed register files and multi-bank register files in the layer of instruction scheduling, software  ...  Register Allocation & Instruction Scheduling In our work, we try to enable ORC compiler flow for PAC embedded VLIW DSP processors.  ... 
doi:10.1145/1254766.1254793 dblp:conf/lctrts/ChenTCLYLL07 fatcat:plonxxe56fdznjhdrludvnahda

Enabling compiler flow for embedded VLIW DSP processors with distributed register files

Chung-Kai Chen, Ling-Hua Tseng, Shih-Chang Chen, Young-Jia Lin, Yi-Ping You, Chia-Han Lu, Jenq-Kuen Lee
2007 SIGPLAN notices  
In this paper, we address the compiler optimization issues for PAC architecture, which is a 5-way issue DSP processor with distributed register files.  ...  We present an integrated flow to address several phases of compiler optimizations in interacting with distributed register files and multi-bank register files in the layer of instruction scheduling, software  ...  Register Allocation & Instruction Scheduling In our work, we try to enable ORC compiler flow for PAC embedded VLIW DSP processors.  ... 
doi:10.1145/1273444.1254793 fatcat:xfvpaws5azehhi2ywm375nkwfm

Synchroscalar: Initial Lessons in Power-Aware Design of a Tile-Based Embedded Architecture [chapter]

John Oliver, Ravishankar Rao, Paul Sultana, Jedidiah Crandall, Erik Czernikowski, Leslie W. Jones, Dean Copsey, Diana Keen, Venkatesh Akella, Frederic T. Chong
2005 Lecture Notes in Computer Science  
Furthermore, statically-scheduled communication and SIMD computation keep control overheads low and energy efficiency high.  ...  This paper describes our initial experiences in designing Synchroscalar, a tile-based embedded architecture targeted for multi-rate signal processing applica tions.  ...  In other words, we want the flexibility of a programmable DSP with energy efficiency more similar to an ASIC.  ... 
doi:10.1007/978-3-540-28641-7_6 fatcat:gzzxtrykwfaqtlbcnskrssgw3u

Observations on Power-Efficiency Trends in Mobile Communication Devices [chapter]

Olli Silvén, Kari Jyrkkä
2005 Lecture Notes in Computer Science  
So far, the improvements of the silicon processes in mobile phones have been exploited by software designers to increase functionality and to cut development time, while usage times, and energy efficiency  ...  Hardware accelerator aware compilation would bridge the software efficiency gap between Fig. 6 .  ...  The accelerators were synchronized with DSP tasks via interrupts. The architecture is ideal for large development teams, but the new functionalities cause some energy overhead.  ... 
doi:10.1007/11512622_16 fatcat:y657ek2c3ve5pjsnm5d2bouq6m

Observations on Power-Efficiency Trends in Mobile Communication Devices

Olli Silven, Kari Jyrkkä
2007 EURASIP Journal on Embedded Systems  
So far, the improvements of the silicon processes in mobile phones have been exploited by software designers to increase functionality and to cut development time, while usage times, and energy efficiency  ...  Hardware accelerator aware compilation would bridge the software efficiency gap between Fig. 6 .  ...  The accelerators were synchronized with DSP tasks via interrupts. The architecture is ideal for large development teams, but the new functionalities cause some energy overhead.  ... 
doi:10.1186/1687-3963-2007-056976 fatcat:4vu54id7nfdjtdbohhkyr7p55e

Observations on Power-Efficiency Trends in Mobile Communication Devices

Olli Silven, Kari Jyrkkä
2007 EURASIP Journal on Embedded Systems  
So far, the improvements of the silicon processes in mobile phones have been exploited by software designers to increase functionality and to cut development time, while usage times, and energy efficiency  ...  Hardware accelerator aware compilation would bridge the software efficiency gap between Fig. 6 .  ...  The accelerators were synchronized with DSP tasks via interrupts. The architecture is ideal for large development teams, but the new functionalities cause some energy overhead.  ... 
doi:10.1155/2007/56976 fatcat:qaf74xxzdjf6bcrwxxkhvqsqlm

Effective Code Generation for Distributed and Ping-Pong Register Files: A Case Study on PAC VLIW DSP Cores

Yung-Chia Lin, Chia Han Lu, Chung-Ju Wu, Chung-Lin Tang, Yi-Ping You, Ya-Chaio Moo, Jenq-Kuen Lee
2007 Journal of Signal Processing Systems  
Our experiences in designing compiler support for the PAC VLIW DSP with irregular resource constraints may also be of interest to those involved in developing compilers for similar architectures.  ...  This paper describes our application of the open research compiler infrastructure to a novel VLIW DSP (known as the PAC DSP core) and the specific design of code generation for its register file architecture  ...  The PAC DSP features an original clustered VLIW architecture that boosts scalability, a feature-rich instruction set with SIMD operation support, a variable-length-instruction encoding scheme, and a large  ... 
doi:10.1007/s11265-007-0059-4 fatcat:wwhl4a3d4vcurpebj3rwh2triq

A flexible approach for compiling scilab to reconfigurable multi-core embedded systems

T. Stripf, O. Oey, T. Bruckschloegl, R. Koenig, M. Huebner, J. Becker, George Goulas, Panayiotis Alefragis, Nikolaos S. Voros, Gerard Rauwerda, Daniel Menard, Olivier Sentieys (+7 others)
2012 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)  
The Architecture oriented par-aLlelization for high performance embedded Multi-core systems using scilAb (ALMA) European project aims to bridge these hurdles through the introduction and exploitation of  ...  The Montium therefore provides an efficient balance between energy, performance, and reuse for embedded platforms for various streaming application with sustained high workloads.  ...  The C compiler later inlines this functions and can unroll the for loops for small arrays with a fixed number of elements.  ... 
doi:10.1109/recosoc.2012.6322879 dblp:conf/recosoc/StripfOBKHBRSKDMKMGAVDMSGP12 fatcat:ztmty66zq5d3hol7j5fenoxcxa

Advancing computer systems without technology progress

Christos Kozyrakis
2013 2013 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)  
2-3x worse area and energy of custom unit  But 8-15x better than SIMD engines, 100x better than multi-core Instruction Graph Fusion/Multi-level Reduction Tree Output Register file SIMD ALUs  ...  Vs. global policies  Interactions with provisioning and pricing models  Implications for application development Advancing Systems without Technology Progress  Locality-aware parallelism  Specialization  ... 
doi:10.1109/ispass.2013.6557164 dblp:conf/ispass/Kozyrakis13 fatcat:futglxnev5bnbfcmxiw54aonyy
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