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2018 Index IEEE Transactions on Computers Vol. 67

2019 IEEE transactions on computers  
., and Rodriguez-Henriquez, F., A Faster Software Implementation of the Supersingular Isogeny Diffie-Hellman Key Exchange Protocol; 1622-1636 Feng, D., see Fu, M., TC Sept. 2018 1259-1272 Analysis  ...  ., þ, TC July 2018 920-933 Energy Optimal Task Scheduling with Normally-Off Local Memory and Sleep-Aware Shared Memory with Access Conflict.  ...  ., þ, TC May 2018 733-739 Energy Optimal Task Scheduling with Normally-Off Local Memory and Sleep-Aware Shared Memory with Access Conflict.  ... 
doi:10.1109/tc.2018.2882120 fatcat:j2j7yw42hnghjoik2ghvqab6ti

Design techniques for low-power systems

Paul J.M Havinga, Gerard J.M Smit
2000 Journal of systems architecture  
We review energy reduction techniques in the architecture and design of a hand-held computer and the wireless communication system, including error control, system decomposition, communication and MAC  ...  We focus on: minimizing capacitance, avoiding unnecessary and wasteful activity, and reducing voltage and frequency.  ...  An energy aware compiler has to make a trade-off between size and speed in favour of energy reduction.  ... 
doi:10.1016/s1383-7621(98)00057-5 fatcat:ytjv3hqq2nal5oyn7cfv276fsu

Memory and Energy Optimization Strategies for Multithreaded Operating System on the Resource-Constrained Wireless Sensor Node

Xing Liu, Kun Hou, Christophe de Vaulx, Jun Xu, Jianfeng Yang, Haiying Zhou, Hongling Shi, Peng Zhou
2014 Sensors  
Not is memory cost optimized, but also the energy cost is optimized in LiveOS, and this is achieved by using the multi-core "context aware" and multi-core "power-off/wakeup" energy conservation approaches  ...  In this article, a new memory-optimized and energy-optimized multithreaded WSN operating system (OS) LiveOS is designed and implemented.  ...  by the French government research program "Investissements d'avenir" through the IMobS3 Laboratory of Excellence (ANR-10-LABX-16-01), by the European Union through the program Regional competitiveness and  ... 
doi:10.3390/s150100022 pmid:25545264 pmcid:PMC4327005 fatcat:37hwrqutzff5fiq2defvi3zybe

Resource-conscious scheduling for energy efficiency on multicore processors

Andreas Merkel, Jan Stoess, Frank Bellosa
2010 Proceedings of the 5th European conference on Computer systems - EuroSys '10  
In multicore systems, shared resources such as caches or the memory subsystem can lead to contention between applications running on different cores, entailing reduced performance and poor energy efficiency  ...  for individual tasks and complete applications.  ...  In the node-local case, KVM spawns normal Linux tasks to host guest VMs, and therefore allows us to directly use our Linux scheduler for both tasks and VMs.  ... 
doi:10.1145/1755913.1755930 dblp:conf/eurosys/MerkelSB10 fatcat:w6fzh44onzefrechytdyt4y7da

Cache Hierarchy-Aware Query Mapping on Emerging Multicore Architectures

Ozcan Ozturk, Umut Orhan, Wei Ding, Praveen Yedlapalli, Mahmut Taylan Kandemir
2017 IEEE transactions on computers  
Most of current commercial multicore systems on the market have on-chip cache hierarchies with multiple layers (typically, in the form of L1, L2 and L3, the last two being either fully or partially shared  ...  A graph partitioning-based method is employed to distribute queries across cores, and an integer linear programming (ILP) formulation is used to address locality and load balancing concerns.  ...  Ding, and P. Yedlapalli were at Pennsylvania State University.  ... 
doi:10.1109/tc.2016.2605682 fatcat:fdfe4mhddrhyfk4isdwak2tkd4

High-Performance Energy-Efficient Multicore Embedded Computing

A. Munir, S. Ranka, A. Gordon-Ross
2012 IEEE Transactions on Parallel and Distributed Systems  
This paper outlines typical requirements of embedded applications and discusses state-of-the-art hardware/software high-performance energy-efficient embedded computing (HPEEC) techniques that help meeting  ...  Finally, we present design challenges and future research directions for HPEEC system development.  ...  ACKNOWLEDGMENTS This work was supported by the Natural Sciences and Engineering Research Council of Canada (NSERC) and the US National Science Foundation (NSF) (CNS-0953447 and CNS-0905308).  ... 
doi:10.1109/tpds.2011.214 fatcat:vagqmojdsjevvc2u2ewqrcjjpq

$C\!\!-\!\!Lock$ : Energy Efficient Synchronization for Embedded Multicore Systems

Seung Hun Kim, Sang Hyong Lee, Minje Jun, Byunghoon Lee, Won Woo Ro, Eui-Young Chung, Jean-Luc Gaudiot
2014 IEEE transactions on computers  
Also, in order to save more energy, disables the clocks of the cores which are blocked for the access to the shared data until the shared data become available.  ...  cause huge overhead with regard to both performance and energy (this is an advantage of locks).  ...  If detects no conflict for the access request, the core proceeds with its tasks with the shared data ([ ]).  ... 
doi:10.1109/tc.2013.84 fatcat:kaigds4epfesjcvthg34wo7z3i

A Survey of Emerging Architectural Techniques for Improving Cache Energy Consumption

Washington Bhebhe, Michael Opoku
2016 Communications on Applied Electronics  
There are encouraging breakthroughs in enhancing CPU performance through fabrication technologies and changes in chip designs but not as much luck has been struck with regards to the computer storage resulting  ...  Needless to mention, the aim of this work is to compile a quick reference guide of energy saving techniques from 2013 to 2016 for engineers, researchers and students.  ...  [72] discuss a low store energy and robust ReRAM-Based flip-flop for normally-off microprocessors. The technique of Normally-of Computing (NoC) benefits microsystems with long sleep time.  ... 
doi:10.5120/cae2016652443 fatcat:hvi6m63qaredfeg3dzecvjws2e

Saving energy by means of dynamic load management in embedded multicore systems

Matthias Becker, Adriaan Schmidt, Martin Orehek, Thomas Nolte
2014 Proceedings of the 9th IEEE International Symposium on Industrial Embedded Systems (SIES 2014)  
Load balancing is widely used to optimize response times and throughput of software systems.  ...  When considering embedded systems, however, additional optimization goals like energy consumption become relevant.  ...  II ADDITIONAL MESSAGES INTRODUCED BY THE LOAD ENERGY AWARENESS EXTENSIONS, INCLUDING THEIR ARGUMENTS Central Scheduler Load Balancing Sleep Request Request to enter sleep state, sent by central scheduler  ... 
doi:10.1109/sies.2014.6871180 dblp:conf/sies/BeckerSON14 fatcat:d6kctgoj5fbwtjblate4gq5oqq

A Survey on Hardware and Software Support for Thread Level Parallelism [article]

Somnath Mazumdar, Roberto Giorgi
2016 arXiv   pre-print
We also review the programming models with respect to their support to shared-memory, distributed-memory and heterogeneity.  ...  Due to the heterogeneity in hardware, hybrid programming model (which combines the features of shared and distributed model) currently has become very promising.  ...  [YHK + 13] quantitatively analyzed that locality-aware scheduling in multicore processors can improve speedup and also reduces the energy cost.  ... 
arXiv:1603.09274v3 fatcat:75isdvgp5zbhplocook6273sq4

Architectural Techniques for Improving the Power Consumption of NoC-Based CMPs: A Case Study of Cache and Network Layer

Emmanuel Ofori-Attah, Washington Bhebhe, Michael Agyeman
2017 Journal of Low Power Electronics and Applications  
The memory design strictly centres on the principle of locality reference, meaning that at any given time, the processor accesses a small or localised region of memory.  ...  The cache memory is a small, high speed memory, which is designed for Static RAM (SRAM) and consists of the most recently accessed data of the main memory.  ...  The technique of normally-off computing benefits microsystems with a long sleep time.  ... 
doi:10.3390/jlpea7020014 fatcat:qgf4zaqltfcgpcd525wuio5dwq

Wireless Caching: Making Radio Access Networks More than Bit-Pipelines

Wei Chen, H. Vincent Poor
2021 Network  
To realize caching, the physical layer and higher layers have to function together, with the aid of prediction and memory units, which substantially broadens the concept of cross-layer design to a multi-unit  ...  Caching has attracted much attention recently because it holds the promise of scaling the service capability of radio access networks (RANs).  ...  Conflicts of Interest: The authors declare no conflict of interest.  ... 
doi:10.3390/network1020010 fatcat:rbg3aomri5aoderpjriwgjkkky

Myrmics: Scalable, Dependency-aware Task Scheduling on Heterogeneous Manycores [article]

Spyros Lyberis, Polyvios Pratikakis, Iakovos Mavroidis, Dimitrios S. Nikolopoulos
2016 arXiv   pre-print
processor of 8 latency-optimized and 512 throughput-optimized CPUs.  ...  memory.  ...  System-wide memory accesses (global) and thread-only accesses (local) are differentiated via the type system. The runtime system interferes to execute global memory accesses.  ... 
arXiv:1606.04282v1 fatcat:c4f7fllpgnctdcf5uxz2kwxuiu

A Survey of Big Data Machine Learning Applications Optimization in Cloud Data Centers and Networks [article]

Sanaa Hamid Mohamed, Taisir E.H. El-Gorashi, Jaafar M.H. Elmirghani
2019 arXiv   pre-print
This survey article reviews the challenges associated with deploying and optimizing big data applications and machine learning algorithms in cloud data centers and networks.  ...  Wide ranging efforts were devoted to optimize systems that handle big data in terms of various applications performance metrics and/or infrastructure energy efficiency.  ...  This work was supported by the Engineering and Physical Sciences Research Council, INTERNET (EP/H040536/1), STAR (EP/K016873/1) and TOWS (EP/S016570/1) projects.  ... 
arXiv:1910.00731v1 fatcat:kvi3br4iwzg3bi7fifpgyly7m4

Improving Resilience to Timing Errors by Exposing Variability Effects to Software in Tightly-Coupled Processor Clusters

Abbas Rahimi, Daniele Cesarini, Andrea Marongiu, Rajesh K. Gupta, Luca Benini
2014 IEEE Journal on Emerging and Selected Topics in Circuits and Systems  
Further, VOMP reaches energy saving of 2%-46% and 15%-50% for tasks, and sections, respectively.  ...  This metadata is made available by carefully placing key data structures in a shared L1 memory and is used by VOMP schedulerss.  ...  The cores have direct access into the off-cluster L2 memory, also mapped in the global address space.  ... 
doi:10.1109/jetcas.2014.2315883 fatcat:emu6fpxpxreyjihdgyxv7xhhde
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