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Enabling application-level performance guarantees in network-based systems on chip by applying dataflow analysis

A. Hansson, M. Wiggers, A. Moonen, K. Goossens, M. Bekooij
2009 IET Computers & Digital Techniques  
To give performance guarantees on the application level, the buffers in the NIs must be sufficiently large for the particular application.  ...  To facilitate real-time applications, networks on chip (NoC) guarantee bounds on latency and throughput. These bounds, however, only extend to the network interfaces (NI), between the IP and the NoC.  ...  Networks on chip (NoC) offer bounds on latency and throughput by reserving resources on the level of connections [7 -10] .  ... 
doi:10.1049/iet-cdt.2008.0093 fatcat:ktuq2jh2kfaoffdfy34bsmmm7m

Mathematical formalisms for performance evaluation of networks-on-chip

Abbas Eslami Kiasari, Axel Jantsch, Zhonghai Lu
2013 ACM Computing Surveys  
performance in Systems-on-Chip.  ...  This article reviews four popular mathematical formalisms-queueing theory, network calculus, schedulability analysis, and dataflow analysis-and how they have been applied to the analysis of on-chip communication  ...  In modern SoCs, the on-chip communication infrastructure or Network-on-Chip (NoC) is a dominant factor for design, validation, and performance analysis.  ... 
doi:10.1145/2480741.2480755 fatcat:wwlsqn7arng7hcgu4lxwbpdf3u

Editorial: Networks on chips

D. Bertozzi, K. Goossens
2009 IET Computers & Digital Techniques  
By distilling the most applicable concepts from this domain and by applying them in a way that suits the constraints of semiconductor design, Networks-on-chip (NoCs) have been proposed as the communication  ...  Editorial Networks on chips Networking has been proven in the computer system arena to be an extremely effective means of managing parallel communication flows in distributed systems.  ...  In 'Enabling Application-Level Performance Guarantees in Network-Based Systems on Chip by Applying Dataflow Analysis', authors A.  ... 
doi:10.1049/iet-cdt.2009.9039 fatcat:u7ijbpjsvnfxzb3rtskmtf7bpa

A clustered manycore processor architecture for embedded and accelerated applications

Benoit Dupont de Dinechin, Renaud Ayrignac, Pierre-Edouard Beaucamps, Patrice Couvert, Benoit Ganne, Pierre Guironnet de Massas, Francois Jacquet, Samuel Jones, Nicolas Morey Chaisemartin, Frederic Riss, Thierry Strudel
2013 2013 IEEE High Performance Extreme Computing Conference (HPEC)  
Each compute cluster and I/O subsystem owns a private address space, while communication and synchronization between them is ensured by data and control Networks-On-Chip (NoC).  ...  In the second case, an explicit parallel programming model based on POSIX processes, threads, and NoC-specific IPC is used.  ...  in order to limit network latencies and guarantee the required bandwidth.  ... 
doi:10.1109/hpec.2013.6670342 dblp:conf/hpec/DinechinABCGMJJCRS13 fatcat:c5m7e2z4knb6fmopfbosjsjnwe

Dataflow formalisation of real-time streaming applications on a Composable and Predictable Multi-Processor SOC

Andrew Nelson, Kees Goossens, Benny Akesson
2015 Journal of systems architecture  
To efficiently execute applications, modern embedded systems contain Globally Asynchronous Locally Synchronous (GALS) processors, network on chip, DRAM and SRAM memories, and system software, e.g. microkernel  ...  Embedded systems often contain multiple applications, some of which have real-time requirements and whose performance must be guaranteed.  ...  Acknowledgements This work was partially funded by projects EU FP7 288008 T-CREST and 288248 Flextiles, CA505 BENEFIC, CA703 OpenES, ARTEMIS-2013-1 621429 EMC2, 621353 DEWI, and the European Social Fund  ... 
doi:10.1016/j.sysarc.2015.04.001 fatcat:wjjajmj5hnbs5d4qc3ebkugcu4

CoMPSoC

Andreas Hansson, Kees Goossens, Marco Bekooij, Jos Huisken
2009 ACM Transactions on Design Automation of Electronic Systems  
These results still apply when the applications are integrated onto the platform, thus separating system-level design and application design.  ...  Performance is analysed per application, using state-of-the-art dataflow techniques or simulation, depending on the requirements of the application.  ...  pressure [Wiggers et al. 2007] , as a result of full buffers, is taken into account, and where we can deliver conservative performance guarantees based on dataflow analysis techniques.  ... 
doi:10.1145/1455229.1455231 fatcat:7xvoht5r45etjcsuhpnjx5xz4e

ReactiFi: Reactive Programming of Wi-Fi Firmware on Mobile Devices [article]

Artur Sterz, Matthias Eichholz, Ragnar Mogk, Lars Baumgärtner, Pablo Graubner, Matthias Hollick, Mira Mezini, Bernd Freisleben
2020 arXiv   pre-print
Our results show that throughput, latency, and power consumption are significantly improved when executing applications on the Wi-Fi chip rather than in the operating system kernel or in user space.  ...  In this paper, we present ReactiFi, a high-level reactive programming language to program Wi-Fi chips on mobile consumer devices.  ...  We show that (i) by executing these applications on the Wi-Fi chip, power consumption can be reduced by up to %, and (ii) by exploiting information that is only available on the Wi-Fi chip, data throughput  ... 
arXiv:2010.00354v1 fatcat:lygneoneanc53i7tsjd264vyky

Conservative application-level performance analysis through simulation of MPSoCs

Andrew Nelson, Andreas Hansson, Henk Corporaal, Kees Goossens
2010 2010 8th IEEE Workshop on Embedded Systems for Real-Time Multimedia  
Applications, often with real-time requirements, are mapped onto Multiprocessor Systems on Chip (MPSoCs).  ...  We introduce a hybrid simulation method which enables performance guarantees on a per-trace basis, without any modelling effort.  ...  We conclude, based on the complexity of the technique and the case study results, that Conservative Simulation is a feasible alternative to Formal Analysis for Application-Level Performance Analysis of  ... 
doi:10.1109/estmed.2010.5666984 dblp:conf/estimedia/NelsonHCG10 fatcat:kokcqobxknbjldzmrwnmpsdqo4

A Generic Architecture for On-Chip Packet-Switched Interconnections [chapter]

Pierre Guerrier, Alain Greiner
2008 Design, Automation, and Test in Europe  
Eventually we present our first results on the cost/performance assessment of an integrated switching network.  ...  This paper presents an architectural study of a scalable system-level interconnection template.  ...  With such process technology, chip designers can create systems-on-a-chip (SoC) by incorporating several dozens of IP blocks, each in the 50-100 kGate range, together with large amounts of embedded DRAM  ... 
doi:10.1007/978-1-4020-6488-3_9 fatcat:5i2isc2k55bolcon3gkqltvj7y

A generic architecture for on-chip packet-switched interconnections

Pierre Guerrier, Alain Greiner
2000 Proceedings of the conference on Design, automation and test in Europe - DATE '00  
Eventually we present our first results on the cost/performance assessment of an integrated switching network.  ...  This paper presents an architectural study of a scalable system-level interconnection template.  ...  With such process technology, chip designers can create systems-on-a-chip (SoC) by incorporating several dozens of IP blocks, each in the 50-100 kGate range, together with large amounts of embedded DRAM  ... 
doi:10.1145/343647.343776 fatcat:7wk4mgcy5rcwpox6ajnqi4rykm

Programmers' views of SoCs

JoAnn M. Paul
2003 Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign & system synthesis - CODES+ISSS '03  
Future SoCs will have multiple heterogeneous processing elements, most likely organized around an on-chip network. Thus, SoCs are increasingly modeled as systems in the large.  ...  New application types will require the chip to be considered programmable along with the individual processing elements on the chip.  ...  Acknowledgements This work was supported in part by ST Microelectronics, General Motors, and the National Science Foundation under Grant 0103706.  ... 
doi:10.1145/944645.944688 dblp:conf/codes/Paul03 fatcat:iz6wyawx3vcbhh6i7fdl7ppa2i

The TERAFLUX Project: Exploiting the DataFlow Paradigm in Next Generation Teradevices

Marco Solinas, Rosa M. Badia, Francois Bodin, Albert Cohen, Paraskevas Evripidou, Paolo Faraboschi, Bernhard Fechner, Guang R. Gao, Arne Garbade, Sylvain Girbal, Daniel Goodman, Behran Khan (+14 others)
2013 2013 Euromicro Conference on Digital System Design  
Thanks to the improvements in semiconductor technologies, extreme-scale systems such as teradevices (i.e., composed by 1000 billion of transistors) will enable systems with 1000+ general purpose cores  ...  per chip, probably by 2020.  ...  ACKNOWLEDGMENTS This work was partly funded by the European FP7 project TERAFLUX (id. 249013) http://www.teraflux.eu. Prof. Avi Mendelson's work has been carried out at Microsoft R&D, Israel.  ... 
doi:10.1109/dsd.2013.39 dblp:conf/dsd/SolinasBBCEFFGGGGKKLLMMNPTUVWWZG13 fatcat:ubsmqg7w3zdi7f3g7i33ng2oce

Virtual execution platforms for mixed-time-criticality systems

Kees Goossens, Ashkan Beyranvand Nejad, Andrew Nelson, Shubhendu Sinha, Arnaldo Azevedo, Karthik Chandrasekar, Manil Dev Gomony, Sven Goossens, Martijn Koedam, Yonghui Li, Davit Mirzoyan, Anca Molnos
2013 ACM SIGBED Review  
Systems on chip (SOC) contain multiple concurrent applications with different time criticality (firm, soft, non realtime).  ...  As a result, they are often developed by different teams or companies, with different models of computation (MOC) such as dataflow, Kahn process networks (KPN), or time-triggered (TT).  ...  This work was partially funded by projects EU FP7 288008 T-CREST and 288248 Flextiles, Catrene CA104 Cobra, and NL STW 10346 NEST.  ... 
doi:10.1145/2544350.2544353 fatcat:lxmodfh25jdrpifqc727rnuija

TERAFLUX: Harnessing dataflow in next generation teradevices

Roberto Giorgi, Rosa M. Badia, François Bodin, Albert Cohen, Paraskevas Evripidou, Paolo Faraboschi, Bernhard Fechner, Guang R. Gao, Arne Garbade, Rahul Gayatri, Sylvain Girbal, Daniel Goodman (+17 others)
2014 Microprocessors and microsystems  
The improvements in semiconductor technologies are gradually enabling extreme-scale systems such as teradevices (i.e., chips composed by 1000 billion of transistors), most likely by 2020.  ...  Our platform comprises 1000+ general purpose cores per chip in order to properly explore the above challenges.  ...  Acknowledgements This work was partly funded by the European FP7 Project TER-AFLUX (id. 249013) http://www.teraflux.eu. Prof. Avi Mendelsons work has been carried out at Microsoft R&D, Israel.  ... 
doi:10.1016/j.micpro.2014.04.001 fatcat:x7zxfxtuxrdvrf67fbljcqiqee

Extended Cyclostatic Dataflow Program Compilation and Execution for an Integrated Manycore Processor

Pascal Aubry, Pierre-Edouard Beaucamps, Frédéric Blanc, Bruno Bodin, Sergiu Carpov, Loïc Cudennec, Vincent David, Philippe Dore, Paul Dubrulle, Benoît Dupont de Dinechin, François Galea, Thierry Goubier (+8 others)
2013 Procedia Computer Science  
As a demonstration of this toolchain, we present an implementation of a H.264 encoder and evaluate its performance on Kalray's embedded manycore MPPA chip.  ...  To solve these programmability issues, there is a renewed interest in the dataflow paradigm.  ...  Some of the emerging solutions are based on dataflow paradigms.  ... 
doi:10.1016/j.procs.2013.05.330 fatcat:4kw6fqbkubdhtnwptin2fai7aq
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