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Embedded intelligent SRAM

Prabhat Jain, G. Edward Suh, Srinivas Devadas
2003 Proceedings of the 40th conference on Design automation - DAC '03  
Many embedded systems use a simple pipelined RISC processor for computation and an on-chip SRAM for data storage.  ...  We present an enhancement called Intelligent SRAM (ISRAM) that consists of a small computation unit with an accumulator that is placed near the on-chip SRAM.  ...  CONCLUSIONS We enhanced embedded system functionality by adding a small computation unit with an accumulator near the onchip SRAM.  ... 
doi:10.1145/776050.776051 fatcat:lbcazi7pgnctbaftcs3atxvazu

Embedded intelligent SRAM

Prabhat Jain, G. Edward Suh, Srinivas Devadas
2003 Proceedings of the 40th conference on Design automation - DAC '03  
Many embedded systems use a simple pipelined RISC processor for computation and an on-chip SRAM for data storage.  ...  We present an enhancement called Intelligent SRAM (ISRAM) that consists of a small computation unit with an accumulator that is placed near the on-chip SRAM.  ...  CONCLUSIONS We enhanced embedded system functionality by adding a small computation unit with an accumulator near the onchip SRAM.  ... 
doi:10.1145/775832.776051 dblp:conf/dac/JainSD03 fatcat:ugrg5ov7szemfhsxxgaqx3ofga

Embedded intelligent SRAM

P. Jain, G.E. Suh, S. Devadas
Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451)  
Many embedded systems use a simple pipelined RISC processor for computation and an on-chip SRAM for data storage.  ...  We present an enhancement called Intelligent SRAM (ISRAM) that consists of a small computation unit with an accumulator that is placed near the on-chip SRAM.  ...  CONCLUSIONS We enhanced embedded system functionality by adding a small computation unit with an accumulator near the onchip SRAM.  ... 
doi:10.1109/dac.2003.1219142 fatcat:bqcbn7pqj5dbvjqakg63vaz4zy

Session 24 Overview: Advanced Embedded Memories

Eric Karl, Shinichiro Shiratake, Jonathan Chang
2021 2021 IEEE International Solid- State Circuits Conference (ISSCC)  
RRAM has emerged as a promising technology for scaling embedded non-volatile memory into advanced nodes; with applications in consumer electronics, self-driving vehicles, intelligent edge devices and more  ...  Advancements in embedded memories continue to enable improvements in system designs spanning from automotive to high-performance computing markets.  ...  RRAM has emerged as a promising technology for scaling embedded non-volatile memory into advanced nodes; with applications in consumer electronics, self-driving vehicles, intelligent edge devices and more  ... 
doi:10.1109/isscc42613.2021.9365820 fatcat:icsmynafhfdqhehzioy2qhzyru

Test/Repair Area Overhead Reduction for Small Embedded SRAMs

Baosheng Wang, Qiang Xu
2006 Proceedings of the Asian Test Symposium  
For current highly-integrated and memory-dominant System-ona-Chips (SoCs), especially for graphics and networking SoCs, the test/repair area overhead of embedded SRAMs (e-SRAMs) is a big concern.  ...  embedded in different functional blocks, test responses compression for wide memories, and various repair strategies for e-SRAMs with different configurations.  ...  Since e-SRAMs are usually deeply embedded onchip and at the same time need to be tested at-speed, Built-in Self-Test (BIST) has become the only practical solution for testing e-SRAMs.  ... 
doi:10.1109/ats.2006.260990 fatcat:utrmd2ju3zaglba5dwoshvqbkm

Exploiting Data Compression for Adaptive Block Placement in Hybrid Caches

Beomjun Kim, Yongtae Kim, Prashant Nair, Seokin Hong
2022 Electronics  
In order to store as many write-intensive blocks in the SRAM region as possible in hybrid caches, an intelligent block placement policy is essential.  ...  This paper proposes an adaptive block placement framework for hybrid caches that incorporates metadata embedding (ADAM).  ...  To this end, several block placement policies have been proposed to intelligently place write-intensive blocks in SRAM regions [3] [4] [5] [6] [7] .  ... 
doi:10.3390/electronics11020240 fatcat:e6niqpn6unhrhkz2uivaff7h2i

MRAM Co-designed Processing-in-Memory CNN Accelerator for Mobile and IoT Applications [article]

Baohua Sun, Daniel Liu, Leo Yu, Jay Li, Helen Liu, Wenhan Zhang, Terry Torng
2018 arXiv   pre-print
More than 40MB MRAM density was embedded into our CNN engines.  ...  Introduction Artificial Intelligence (AI) is recognized as one of the key technology in the Fourth Industrial Revolution.  ... 
arXiv:1811.12179v1 fatcat:zbzwroyotffrrcjxpgnl5rwhxa

Embedded Multiport Data Buffer for a Solid-State Drive Controller

Hailuan Liu, Lingyan Fan, Jianjun Luo, Guorui Feng
2021 IEICE Electronics Express  
SRAM cells created by the IC foundry as a standard module are embedded in the SSD controller as data buffer and can be single-port or two-port.  ...  Solid-state drives (SSDs) for mobile and embedded systems may not provide very high performance by today's standards; however, they are small, low cost and consume little power.  ...  In this study, an SSD controller is designed without attached DRAM but with embedded SRAM.  ... 
doi:10.1587/elex.18.20210132 fatcat:lk3bxw5vgjeutklnqbv4ladnfa

An Embedded 8-bit RISC Controller for Yield Enhancement of the 90-nm PRAM

Hyejung Kim, Kyomin Sohn, Jerald Yoo, Hoi-Jun Yoo
2007 2007 IEEE Custom Integrated Circuits Conference  
The embedded RISC enables 100Mb/s/pin read/write throughputs to PRAM.  ...  An embedded 8b RISC for advanced memories is designed to control, analyze and optimize the memory timing and voltage parameters.  ...  In mode (2), the PRAM operates in burst read/write mode by using RISC and cache-like SRAM blocks. Mode (3) is for setup and test by accessing the embedded SRAM and the MRS.  ... 
doi:10.1109/cicc.2007.4405847 dblp:conf/cicc/KimSYY07 fatcat:c6jbvdsojvf5pdndgclppmypum

MC-CIM: Compute-in-Memory with Monte-Carlo Dropouts for Bayesian Edge Intelligence [article]

Priyesh Shukla, Shamma Nasrin, Nastaran Darabi, Wilfred Gomes, Amit Ranjan Trivedi
2021 arXiv   pre-print
We propose MC-CIM, a compute-in-memory (CIM) framework for robust, yet low power, Bayesian edge intelligence.  ...  Proposed MC-CIM with 16x31 SRAM array, 0.85 V supply, 16nm low-standby power (LSTP) technology consumes 27.8 pJ for 30 MC-Dropout instances of probabilistic inference in its most optimal computing and  ...  Figure 4 : 4 Figure 4: (a) SRAM-embedded random dropout bit generator. (b) Dropout probability calibration in CIM-embedded RNG.  ... 
arXiv:2111.07125v1 fatcat:n5zbimhq5vbztcxw7dej2fmv4a

Instruction cache locking inside a binary rewriter

Kapil Anand, Rajeev Barua
2009 Proceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems - CASES '09  
of Embedded Systems CPU External DRAM Internal SRAM Fast Small Slow Large Internal SRAM Techniques • Hardware Cache CPU External DRAM Internal SRAM Cache Hardware Management  ...  Internal SRAM should be managed intelligently • Introduction • Motivation • Cache Locking Problem • Algorithm -Binary Rewriter • Experiment and Results • Summary Outline 3 Memory Architecture  ... 
doi:10.1145/1629395.1629422 dblp:conf/cases/AnandB09 fatcat:jytnytlzbjhyddb7rnmwymqegi

High Speed Novel Design of Sram for Highly Reliable Applications

2019 VOLUME-8 ISSUE-10, AUGUST 2019, REGULAR ISSUE  
Power consumption is the key parameter for an SRAM memory design (SRAM). New tag generation system designed for integrity checking of SRAM.  ...  In this paper, the design of novel SRAM is implemented for the highly reliable applications. For high-speed memory applications such as cache, a SRAM is often used.  ...  There are delicate mistakes happened in the SRAM cell, to Delimitate these blunders we utilize the bit interleaving SRAM engineering.Published By: Blue Eyes Intelligence Engineering & Sciences Publication  ... 
doi:10.35940/ijitee.b1029.1292s319 fatcat:te445xfbczeg3g4omgj2sqiu6m

DESIGN OF SRAM ARCHITECTURE WITH LOW POWER WITHOUT AFFECTING SPEED USING FINFET

Mr.S.Mohammed Sulaiman, B. Jaison, M.Anto Bennet, M. Vijay, V.Pandi Selvam, P. Anandakumar
2017 International Journal on Smart Sensing and Intelligent Systems  
To overcome the disadvantage of the average 8T SRAM architecture, the 6T SRAM Design is proposed.  ...  Its leads to the reduction of read stability of the SRAM Design. In that case, the gate terminal of the SRAM Architecture is not connected to the buffer results a large delay.  ...  The amount of embedded SRAM in modern Systems on-Chips (SoC) increases to meet the performance requirements in each technology generation [3] .  ... 
doi:10.21307/ijssis-2017-253 fatcat:dhg5jd6y7fdlnptc4eisrqhs3m

Openmv: A Python powered, extensible machine vision camera [article]

Ibrahim Abdelkader, Yasser El-Sonbaty, Mohamed El-Habrouk
2017 arXiv   pre-print
The uniqueness of this platform lies in running an embedded Python3 interpreter, allowing its peripherals and machine vision library to be scripted in Python.  ...  It has become possible to perform complex in-network image processing using low-power embedded smart cameras, enabling a multitude of new collaborative image processing applications.  ...  Pixy (CMUCam5) Mesheye MeshEye (Hengstler et al, 2007 ) is a smart stereo-camera targeted at intelligent surveillance applications.  ... 
arXiv:1711.10464v1 fatcat:md2v7sqlyjhv7npfwkremoqo2e

Memory-based Combination PUFs for Device Authentication in Embedded Systems [article]

Soubhagya Sutar, Arnab Raha, Vijay Raghunathan
2017 arXiv   pre-print
In this paper, we propose the design of a new memory-based combination PUF that intelligently combines two memory technologies, SRAM and DRAM, to overcome these shortcomings.  ...  Embedded systems play a crucial role in fueling the growth of the Internet-of-Things (IoT) in application domains such as healthcare, home automation, transportation, etc.  ...  Replacing Genuine DRAM with a Counterfeit: A Case-Study Several embedded systems contain DRAMs in the form of Dual In-line Memory Modules (DIMMs) that (unlike SRAMs, which are physically soldered) could  ... 
arXiv:1712.01611v1 fatcat:jwx4m6bj6vdhhbidsos6ltkxum
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