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Eliminating microarchitectural dependency from Architectural Vulnerability

Vilas Sridharan, David R. Kaeli
2009 2009 IEEE 15th International Symposium on High Performance Computer Architecture  
To evaluate the behavior of software in the presence of hardware faults, we must isolate the software-dependent (architecture-level masking) portion of AVF from the hardware-dependent (microarchitecture-level  ...  AVF captures both microarchitectural and architectural fault masking effects; therefore, AVF measurements cannot generate insight into the vulnerability of software independent of hardware.  ...  As shown in Figure 1 , this means that AVF is dependent on software (architecture) as well as hardware (microarchitecture).  ... 
doi:10.1109/hpca.2009.4798243 dblp:conf/hpca/SridharanK09 fatcat:jqmaxue4yfeipikmvbifrpa24u

Ozone: Efficient Execution with Zero Timing Leakage for Modern Microarchitectures [article]

Zelalem Birhanu Aweke, Todd Austin
2017 arXiv   pre-print
To provide a means for total protection from timing-based side-channel attacks, we develop Ozone, the first zero timing leakage execution resource for a modern microarchitecture.  ...  In this work, we show that the state-of-the-art techniques in timing side-channel protection, which limit timing leakage but do not eliminate it, still have significant vulnerabilities to timing-based  ...  It uses conditional move instructions such as the CMOVcc instruction from the x86 architecture [10] to eliminate conditional branches.  ... 
arXiv:1703.07706v1 fatcat:sc7qhi47lzfqzlabm55gnghouy

Relational Models of Microarchitectures for Formal Security Analyses [article]

Nicholas Mosier, Hanna Lachnitt, Hamed Nemati, Caroline Trippel
2021 arXiv   pre-print
First, we demonstrate that our leakage definition faithfully captures a sampling of (transient and non-transient) microarchitectural attacks from the literature.  ...  Second, we develop a static analysis tool based on LCMs which automatically identifies Spectre vulnerabilities in programs and scales to analyze realistic-sized codebases, like libsodium.  ...  Finally, Blade [69] uses a static type system to eliminate transient leakage from CT cryptographic code.  ... 
arXiv:2112.10511v1 fatcat:ylcaex3mxfatrl2sezl5hl2iha

Where Does Security Stand? New Vulnerabilities vs. Trusted Computing

Shay Gueron, Jean-Pierre Seifert, Geoffrey Strongin, Derek Chiou, Resit Sendag, Joshua J. Yi
2007 IEEE Micro  
The quality of the microarchitecture is measured by the efficiency from the performance, power consumption, and cost.  ...  Innovations in the microarchitectural features improve the processor's quality from the power/performance viewpoint.  ...  He has a PhD in applied mathematics from Technion-Israel Institute of Technology.  ... 
doi:10.1109/mm.2007.112 fatcat:jbtthgvd5bewxlt52u36kkur5i

Characterizing the effects of transient faults on a high-performance processor pipeline

N.J. Wang, J. Quek, T.M. Rafacz, S.J. Patel
2004 International Conference on Dependable Systems and Networks, 2004  
Together, the baseline microarchitectural substrate and software mask more than 9 out of 10 transient faults from affecting correct program execution.  ...  These failures were analyzed to identify the most vulnerable portions of the processor, which were then protected using simple low-overhead techniques. This resulted in a 75% reduction in failures.  ...  This work was supported by the C2S2 Marco center, NSF grant EIA-0224453, and equipment donation from AMD.  ... 
doi:10.1109/dsn.2004.1311877 dblp:conf/dsn/WangQRP04 fatcat:szmof2m3bzaj5bxwyoupiembki

Revizor: Testing Black-box CPUs against Speculation Contracts [article]

Oleksii Oleksenko, Christof Fetzer, Boris Köpf, Mark Silberstein
2021 arXiv   pre-print
Such vulnerabilities often stay undetected for a long time as we lack the tools for systematic testing of CPUs to find them.  ...  In this paper, we propose an approach to automatically detect microarchitectural information leakage in commercial black-box CPUs.  ...  Introduction The instruction set architecture (ISA) specifies the functional behavior of a CPU but abstracts from its implementation details (microarchitecture).  ... 
arXiv:2105.06872v2 fatcat:ul5ljrrk3zdupp2j53a62orw5u

Microarchitecture soft error vulnerability characterization and mitigation under 3D integration technology

Wangyuan Zhang, Tao Li
2008 2008 41st IEEE/ACM International Symposium on Microarchitecture  
In this work, we make the first attempt to characterize microarchitecture soft error vulnerabilities across the stacked chip layers under 3D integration technologies.  ...  We showcase that the first characteristic allows outer-layers to shield inter-layers from particle strikes and the second feature enables the deployment of error resilience device techniques (e.g.  ...  By applying the SOI technology only at the most vulnerable layer in a 4-layer 3D microarchitecture design, we can achieve the desired reliability target while eliminating a significant portion (75%) of  ... 
doi:10.1109/micro.2008.4771811 dblp:conf/micro/ZhangL08 fatcat:qcjhfcm2wngrpfmxw57srdyrv4

Processor Hardware Security Vulnerabilities and their Detection by Unique Program Execution Checking [article]

Mohammad Rahmani Fadiheh, Dominik Stoffel, Clark Barrett, Subhasish Mitra, Wolfgang Kunz
2018 arXiv   pre-print
by staying away from high-end processors.  ...  Many sources believe that such covert channels are intrinsic to highly advanced processor architectures based on speculation and out-of-order execution, suggesting that such security risks can be avoided  ...  Vulnerabilities can emerge from HW/SW interaction or from the hardware itself.  ... 
arXiv:1812.04975v1 fatcat:rlrjzmclinh43h72u6y3tt6la4

A Survey of Microarchitectural Side-channel Vulnerabilities, Attacks and Defenses in Cryptography [article]

Xiaoxuan Lou, Tianwei Zhang, Jun Jiang, Yinqian Zhang
2021 arXiv   pre-print
of side-channel vulnerabilities.  ...  One popular type of such attacks is the microarchitectural attack, where the adversary exploits the hardware features to break the protection enforced by the operating system and steal the secrets from  ...  Therefore, effective elimination of side-channel vulnerabilities has been a long-standing goal.  ... 
arXiv:2103.14244v1 fatcat:u35eyivqbngplfa4qrswfsqqti

An Exhaustive Approach to Detecting Transient Execution Side Channels in RTL Designs of Processors [article]

Mohammad Rahmani Fadiheh, Alex Wezel, Johannes Mueller, Joerg Bormann, Sayak Ray, Jason M. Fung, Subhasish Mitra, Dominik Stoffel, Wolfgang Kunz
2021 arXiv   pre-print
Despite recent advances, understanding the intricate implications of microarchitectural design decisions on processor security remains a great challenge and has caused a number of update cycles in the  ...  UPEC does not exploit any a priori knowledge on known attacks and can therefore detect also vulnerabilities based on new, so far unknown, types of channels.  ...  The microarchitectural observation can be obtained from the microarchitectural execution by keeping in the sequence all valuations to the architectural registers at the time points they are written (due  ... 
arXiv:2108.01979v2 fatcat:bb2ivpd5irczzexro2yqvm547u

A case for exposing extra-architectural state in the ISA

Jason Lowe-Power, Venkatesh Akella, Matthew K. Farrens, Samuel T. King, Christopher J. Nitta
2018 Proceedings of the 7th International Workshop on Hardware and Architectural Support for Security and Privacy - HASP '18  
Rather than exploiting an incorrect implementation of the ISA, these attacks leverage the undocumented implementationspecific speculation behavior of high-performance microarchitectures to affect the extra-architectural  ...  We hope this new framework will give architects and security researchers tools to reduce the likelihood of future surprise vulnerabilities.  ...  Specifically, the address in array2 that is evicted from the cache depends on the value of the out-of-bounds accesses, leaking secret information.  ... 
doi:10.1145/3214292.3214300 dblp:conf/isca/Lowe-PowerAFKN18 fatcat:q2bwq5fayrcu7iikpfiprttf2i

Optimizing Issue Queue Reliability to Soft Errors on Simultaneous Multithreaded Architectures

Xin Fu, Wangyuan Zhang, Tao Li, José Fortes
2008 2008 37th International Conference on Parallel Processing  
In this paper, we explore microarchitecture techniques to optimize IQ reliability to soft error on SMT architectures.  ...  Extensive simulation results show that, on average, our microarchitecture level soft error mitigation techniques can significantly reduce IQ vulnerability by 42% with 1% performance improvement.  ...  In this paper, we explore reliability-aware microarchitecture optimizations to mitigate IQ soft error vulnerability on SMT architectures.  ... 
doi:10.1109/icpp.2008.23 dblp:conf/icpp/FuZLF08 fatcat:zk27gnhemrbcdglrcw2xdfbghu

NoSQ: Store-Load Communication without a Store Queue

Tingting Sha, Milo M.K. Martin, Amir Roth
2007 IEEE Micro  
Acknowledgments NSF Career award CCF-0238203, NSF CPA grant CCF-0541292, and donations from Intel supported this work.  ...  His research interests include computer architecture and microarchitecture. Roth has a PhD in computer science from the University of Wisconsin-Madison. He is a member of the ACM and the IEEE.  ...  His research interests include scalable microarchitectures, multiprocessor computer architectures, memory systems, and verification.  ... 
doi:10.1109/mm.2007.17 fatcat:sbzoag742nbozpqjioodroxzfe

Soft error vulnerability aware process variation mitigation

Xin Fu, Tao Li, Jose A. B. Fortes
2009 2009 IEEE 15th International Symposium on High Performance Computer Architecture  
It tolerates the deleterious impact of variable latency techniques on soft error reliability by reducing the quantity and residency cycle of vulnerable bits in the microarchitecture structure at a fine  ...  We explore two techniques that can effectively mitigate the effect of design parameter variation while significantly enhancing microarchitecture soft error reliability.  ...  level), mainly determined by circuit design and process technology, and the architecture vulnerability factor (AVF) 1.  ... 
doi:10.1109/hpca.2009.4798241 dblp:conf/hpca/FuLF09 fatcat:ghsflmtfv5ajbausi567pqf6be

Exploiting Hardware Vulnerabilities to Attack Embedded System Devices: a Survey of Potent Microarchitectural Attacks

Apostolos Fournaris, Lidia Pocero Fraile, Odysseas Koufopavlou
2017 Electronics  
Apart from the software vulnerabilities that typical malicious programs use, there are some very interesting hardware vulnerabilities that can be exploited in order to mount devastating software or hardware  ...  Real-time microarchitecture attacks such as the cache side-channel attacks are such case but also the newly discovered Rowhammer fault injection attack that can be mounted even remotely to gain full access  ...  Fournaris conceived and structured the paper's concept, did the overview on cache35 attacks, side channel attacks and countermeasures and contributed to the survey research of the rowhammer microarchitectural  ... 
doi:10.3390/electronics6030052 fatcat:7twtik7awjdcrk62xzbaqkaq4y
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