Filters








5,214 Hits in 4.9 sec

Elastic-buffer flow control for on-chip networks

George Michelogiannakis, James Balfour, William J. Dally
2009 2009 IEEE 15th International Symposium on High Performance Computer Architecture  
This paper presents elastic buffers (EBs), an efficient flow-control scheme that uses the storage already present in pipelined channels in place of explicit input virtualchannel buffers (VCBs).  ...  Using EBs results in up to 8% (12% for low-swing channels) improvement in peak throughput per unit power compared to a VC flow-control network.  ...  This paper presents elastic buffers (EBs), an efficient flow-control scheme that uses the storage already present in pipelined channels instead of input virtual-channel buffers (VCBs).  ... 
doi:10.1109/hpca.2009.4798250 dblp:conf/hpca/MichelogiannakisBD09 fatcat:7ivcctirpzfl5dqlydz3hgyrj4

Elastic Buffer Flow Control for On-Chip Networks

George Michelogiannakis, William J. Dally
2013 IEEE transactions on computers  
This paper presents elastic buffers (EBs), an efficient flow-control scheme that uses the storage already present in pipelined channels in place of explicit input virtualchannel buffers (VCBs).  ...  Using EBs results in up to 8% (12% for low-swing channels) improvement in peak throughput per unit power compared to a VC flow-control network.  ...  This paper presents elastic buffers (EBs), an efficient flow-control scheme that uses the storage already present in pipelined channels instead of input virtual-channel buffers (VCBs).  ... 
doi:10.1109/tc.2011.237 fatcat:n2ihebuq6rhtvjfet7segrioie

Realization of Efficient High Throughput Buffering Policies for Network on Chip Router

Liyaqat Nazir, Roohie Naaz Mir
2016 International Journal of Computer Network and Information Security  
Elastic buffer (EB) flow control is a simple control logic in the channels to use pipeline flipflops (FFs) as storage locations.  ...  Her current research interests include Reconfigurable computing, security and routing in wireless adhoc networks, Sensor networks, High level computer architecture design Network on chip, Digital VLSI  ...  Further work is aimed to implement other buffering policies, alternative full throughput elastic buffers full generic elastic buffer and evaluate them for credit based flow control protocol used in NoC  ... 
doi:10.5815/ijcnis.2016.07.08 fatcat:sgrwnun4knapxeftfyrn2xbaki

Kilo-NOC

Boris Grot, Joel Hestness, Stephen W. Keckler, Onur Mutlu
2011 Proceeding of the 38th annual international symposium on Computer architecture - ISCA '11  
We further improve network area-and energy-efficiency through a novel flow control mechanism that enables a single-network, low-cost elastic buffer implementation.  ...  In this paper, we propose and evaluate technologies to enable networks-on-chip (NOCs) to support a thousand connected components (Kilo-NOC) with high area and energy efficiency, good performance, and strong  ...  Acknowledgments We wish to thank Naveen Muralimanohar, Emmett Witchel, and Andrew Targhetta for their contributions to this paper.  ... 
doi:10.1145/2000064.2000112 dblp:conf/isca/GrotHKM11 fatcat:3vveq3tdcjfxdgtfj553kjgq5i

Kilo-NOC

Boris Grot, Joel Hestness, Stephen W. Keckler, Onur Mutlu
2011 SIGARCH Computer Architecture News  
We further improve network area-and energy-efficiency through a novel flow control mechanism that enables a single-network, low-cost elastic buffer implementation.  ...  In this paper, we propose and evaluate technologies to enable networks-on-chip (NOCs) to support a thousand connected components (Kilo-NOC) with high area and energy efficiency, good performance, and strong  ...  Acknowledgments We wish to thank Naveen Muralimanohar, Emmett Witchel, and Andrew Targhetta for their contributions to this paper.  ... 
doi:10.1145/2024723.2000112 fatcat:vidtu6m7evc43lviuuassnggyq

A QoS-Enabled On-Die Interconnect Fabric for Kilo-Node Chips

B. Grot, J. Hestness, S. Keckler, O. Mutlu
2012 IEEE Micro  
Elastic-buffer flow control Freed from the burden of enforcing QoS, routers outside of shared regions enjoy a significant reduction in VCs to just one VC per packet class.  ...  Although conventional elastic-buffered networks are incompatible with QoS due to the serializing nature of EB flow control (which can cause priority inversion within a channel), our proposed TAQ architecture  ...  His research focuses on processor architectures, memory systems, and interconnection networks for high-throughput, energy-aware computing.  ... 
doi:10.1109/mm.2012.18 fatcat:msq2d63y3bbmvgg5e3udtfbrhe

Performance Evaluation of Elastic GALS Interfaces and Network Fabric

Junbok You, Yang Xu, Hosuk Han, Kenneth S. Stevens
2008 Electronical Notes in Theoretical Computer Science  
This paper reports on the design of a test chip built to test a) a new latency insensitive network fabric protocol and circuits, b) a new synchronizer design, and c) how efficiently one can synchronize  ...  Buffering at the synchronization points are required to allow for variability in clocking frequencies and correct data transmission.  ...  There are various classes of such protocols but all use a handshaking protocol similar to traditional asynchronous design to implement flow control and data buffering.  ... 
doi:10.1016/j.entcs.2008.02.004 fatcat:hijw53uqurda7abbs5u7el7zze

Network Simplicity for Latency Insensitive Cores

Daniel Gebhardt, JunBok You, W. Scott Lee, Kenneth S. Stevens
2008 Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008)  
These types of cores provide native flow control that is compatible with this network, thus reducing adapter overhead and buffering needs by applying backpressure directly to the sending core.  ...  We show that under realistic traffic patterns our sample network meets performance requirements and uses less power compared to a similar design.  ...  A network compatible with elastic protocols yields very efficient circuits and there is no need for extra flow-control logic in the core's network adapter, nor extra NACK control messages.  ... 
doi:10.1109/nocs.2008.4492741 fatcat:vbdorcwy3vcm5fy2yneocatyii

ATLAS I: implementing a single-chip ATM switch with backpressure

G. Kornaros, D. Pnevmatikatos, P. Vatsolaki, G. Kalokerinos, C. Xanthaki, D. Mavroidis, D. Serpanos, M. Katevenis
1999 IEEE Micro  
networks with credit-based flow control at a reasonable cost.  ...  IEEE MICRO Credit-based flow control, also called backpressure, leads to network architectures that never drop data.  ...  , but also to develop network mechanisms that integrate rate-based and credit-based flow control efficiently and effectively.  ... 
doi:10.1109/40.748794 fatcat:hpnplpuprvek5jntncqcwfoq6u

DESA: Distributed Elastic Switch Architecture for efficient networks-on-FPGAS

Antoni Roca, Jose Flich, Giorgos Dimitrakopoulos
2012 22nd International Conference on Field Programmable Logic and Applications (FPL)  
The proposed switch operates as an elastic pipeline and can be spread throughout the FPGA chip irrespective the topology of the network and without limiting the placement options of the corresponding EDA  ...  Networks-on-FPGA consist of a network of switches connected with point-to-point links and can cover sufficiently the communication needs of complex systems implemented on FPGA platforms.  ...  The first on-chip interconnection networks mimicked the designs that were architected for large, high performance multiprocessors.  ... 
doi:10.1109/fpl.2012.6339135 dblp:conf/fpl/RocaFD12 fatcat:uy53v6564vfpjclv2ypzlgvzpq

ElastiStore: An elastic buffer architecture for Network-on-Chip routers

I. Seitanidis, A. Psarras, G. Dimitrakopoulos, C. Nicopoulos
2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2014  
The design of scalable Network-on-Chip (NoC) architectures calls for new implementations that achieve highthroughput and low-latency operation, without exceeding the stringent area-energy constraints of  ...  modern Systems-on-Chip (SoC).  ...  Elastic buffering assumes only one form of handshake on each network channel that cannot distinguish between different flows thus making its operation serial in nature.  ... 
doi:10.7873/date.2014.253 dblp:conf/date/SeitanidisPDN14 fatcat:f7v5xtzavfbjdfzejwpngkiaha

ElastiStore: Flexible Elastic Buffering for Virtual-Channel-Based Networks on Chip

Ioannis Seitanidis, Anastasios Psarras, Kypros Chrysanthou, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos
2015 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
Index Terms-Buffer sharing, elastic buffering (EB), network on chip (NoC), virtual channels (VCs), VLSI.  ...  The network on chip (NoC) is expected to undertake the expanding demands of the ever-increasing numbers of processing elements, while its area/power footprint remains severely constrained.  ...  On the contrary, an elastic flow-control policy allows all empty stages to be filled with incoming data.  ... 
doi:10.1109/tvlsi.2014.2383442 fatcat:rfvqznifgffthkkhgvz7vv4ywe

Centralized buffer router: A low latency, low power router for high radix NOCs

Syed Minhaj Hassan, Sudhakar Yalamanchili
2013 2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS)  
While router buffers have been used as performance multipliers, they are also major consumers of area and power in on-chip networks.  ...  In this paper, we propose centralized elastic bubble router -a router micro-architecture based on the use of centralized buffers (CB) with elastic buffered (EB) links.  ...  Elastic buffered links are used to provide link level flow control. A fundamental problem with elastic buffer flow control is that they face challenges in providing multiple virtual channels.  ... 
doi:10.1109/nocs.2013.6558397 dblp:conf/nocs/HassanY13 fatcat:agndczl4tjcr3kj2puaai5n2iu

A Programmable Adaptive Router for a GALS Parallel System

Jian Wu, Steve Furber, Jim Garside
2009 2009 15th IEEE Symposium on Asynchronous Circuits and Systems  
The design objectives are achieved through the use of a synchronous elastic pipeline controlled by a handshake protocol which gives the flexibility to stall the traffic flow during run-time for configuration  ...  This paper describes a router which is the key component of a scalable asynchronous on-chip and inter-chip communication infrastructure for an application-specific parallel computing system.  ...  The authors are grateful for this support.  ... 
doi:10.1109/async.2009.17 dblp:conf/async/WuFG09 fatcat:vlsrmyjtd5d4teqallh6mvd3ju

Elastic Flow in an Application Specific Network-on-Chip

Daniel Gebhardt, Kenneth S. Stevens
2008 Electronical Notes in Theoretical Computer Science  
The nature of elastic-flow removes the need for large router buffers, and thus we gain a significant power and space advantage compared to traditional NoCs.  ...  A Network-on-Chip (NoC) is increasingly needed to interconnect the large number and variety of Intellectual Property (IP) cells that make up a System-on-Chip (SoC).  ...  Latency in a clocked network will be equivalent in cycles to the number of buffers on a path between the sender and receiver -be they routers or elastic half buffers.  ... 
doi:10.1016/j.entcs.2008.02.003 fatcat:7nf2swfzyjdifhkjrmo2cykegy
« Previous Showing results 1 — 15 out of 5,214 results