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Elastic Refresh: Techniques to Mitigate Refresh Penalties in High Density Memory

Jeffrey Stuecheli, Dimitris Kaseridis, Hillery C.Hunter, Lizy K. John
2010 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture  
High density memory is becoming more important as many execution streams are consolidated onto single chip many-core processors.  ...  The proposed mechanisms are shown to mitigate much of the penalties seen with dense DRAM devices.  ...  ACKNOWLEDGEMENTS The authors would like to thank Steve Dodson, Warren Maule, Kyu-Hyoun Kim, and the anonymous reviewers for their suggestions that helped improve the quality of this paper.  ... 
doi:10.1109/micro.2010.22 dblp:conf/micro/StuecheliKHJ10 fatcat:ovzb6ogo4zfjnfr22uo3xjhnle

Coordinated refresh: Energy efficient techniques for DRAM refresh scheduling

Ishwar Bhati, Zeshan Chishti, Bruce Jacob
2013 International Symposium on Low Power Electronics and Design (ISLPED)  
To reduce refresh penalty we propose techniques referred collectively as "Coordinated Refresh", in which scheduling of low power modes and refresh commands are coordinated so that most of the required  ...  refreshes are issued when the DRAM device is in the deepest low power Self Refresh (SR) mode.  ...  However, DR does not address the increasing refresh penalty in high density devices.  ... 
doi:10.1109/islped.2013.6629295 dblp:conf/islped/BhatiCJ13 fatcat:bkv55kyft5eytbfas7uxp6fhte

Reducing DRAM Refresh Overheads with Refresh-Access Parallelism [article]

K. K. Chang, D. Lee, Z. Chishti, A. R. Alameldeen, C. Wilkerson, Y. Kim, O. Mutlu
2018 arXiv   pre-print
The goal is to address the drawbacks of state-of-the-art per-bank refresh mechanism by building more efficient techniques to parallelize refreshes and accesses within DRAM.  ...  First, instead of issuing per-bank refreshes in a round-robin order, as it is done today, DARP issues per-bank refreshes to idle banks in an out-of-order manner.  ...  Acknowledgments We thank Saugata Ghose for his dedicated e ort in the preparation of this article.  ... 
arXiv:1805.01289v1 fatcat:fwwi4pdh3fhdhf2j4og44itmp4

Refresh pausing in DRAM memory systems

Prashant J. Nair, Chia-Chen Chou, Moinuddin K. Qureshi
2014 ACM Transactions on Architecture and Code Optimization (TACO)  
This article provides an alternative and scalable option to reduce the latency penalty due to refresh.  ...  As the capacity of DRAM memories has increased, so has the amount of time consumed in doing refresh.  ...  REFRESH PAUSING VERSUS REFRESH SCHEDULING We proposed Refresh Pausing to mitigate refresh-related latency penalties.  ... 
doi:10.1145/2579669 fatcat:nctztd5bsrenzbaf6wy3a4jrtq

Flexible auto-refresh

Ishwar Bhati, Zeshan Chishti, Shih-Lien Lu, Bruce Jacob
2015 Proceedings of the 42nd Annual International Symposium on Computer Architecture - ISCA '15  
In this paper, we show that even when skipping a high percentage of refresh operations, existing row-granurality refresh techniques are mostly ineffective due to the inherent efficiency disparity between  ...  We show that these modifications allow a memory controller to reduce as many refreshes as in prior work,  ...  Acknowledgements The authors would like to thank David Wang, Mu-Tien Chang, and the anonymous reviewers for their valuable inputs.  ... 
doi:10.1145/2749469.2750408 dblp:conf/isca/BhatiCLJ15 fatcat:4fy7jmmcnffwphnn4yszpbuiaa

Flexible auto-refresh

Ishwar Bhati, Zeshan Chishti, Shih-Lien Lu, Bruce Jacob
2015 SIGARCH Computer Architecture News  
In this paper, we show that even when skipping a high percentage of refresh operations, existing row-granurality refresh techniques are mostly ineffective due to the inherent efficiency disparity between  ...  We show that these modifications allow a memory controller to reduce as many refreshes as in prior work,  ...  Acknowledgements The authors would like to thank David Wang, Mu-Tien Chang, and the anonymous reviewers for their valuable inputs.  ... 
doi:10.1145/2872887.2750408 fatcat:6sax4oe3ljcfhijy3lcqdliyhy

A case for Refresh Pausing in DRAM memory systems

P. Nair, Chia-Chen Chou, M. K. Qureshi
2013 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA)  
DRAM cells rely on periodic refresh operations to maintain data integrity. As the capacity of DRAM memories has increased, so has the amount of time consumed in doing refresh.  ...  This paper provides an alternative and scalable option to reduce the latency penalty due to refresh.  ...  Acknowledgments Thanks to Jeff Stuecheli and Rajeev Balasubramonian for discussions and feedback. Moinuddin Qureshi is supported by NetApp Faculty Fellowship and Intel Early Career Award.  ... 
doi:10.1109/hpca.2013.6522355 dblp:conf/hpca/NairCQ13 fatcat:mdxxxpqkh5cktbhgkzlfsl2m2y

Improving DRAM performance by parallelizing refreshes with accesses

Kevin Kai-Wei Chang, Donghyuk Lee, Zeshan Chishti, Alaa R. Alameldeen, Chris Wilkerson, Yoongu Kim, Onur Mutlu
2014 2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA)  
The goal is to address the drawbacks of per-bank refresh by building more efficient techniques to parallelize refreshes and accesses within DRAM.  ...  First, instead of issuing per-bank refreshes in a round-robin order, DARP issues per-bank refreshes to idle banks in an out-of-order manner.  ...  This research was supported in part by the Intel Science and Technology Center on Cloud Computing, SRC (Semiconductor Research Corporation), and an NSF CAREER Award 0953246.  ... 
doi:10.1109/hpca.2014.6835946 dblp:conf/hpca/ChangLCAWKM14 fatcat:rugsbdsolrftxjjj6j775yozwi

CREAM: A Concurrent-Refresh-Aware DRAM Memory architecture

Tao Zhang, Matt Poremba, Cong Xu, Guangyu Sun, Yuan Xie
2014 2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA)  
To mitigate the refresh penalty, a Concurrent-REfresh-Aware Memory system (CREAM) is proposed in this work so that memory access and refresh can be served in parallel.  ...  As DRAM density keeps increasing, more rows need to be protected in a single refresh with the constant refresh number.  ...  Consequently, the DRAM system should be carefully designed to mitigate the refresh penalty.  ... 
doi:10.1109/hpca.2014.6835947 dblp:conf/hpca/ZhangPXSX14 fatcat:lpwxedokhne7pa6bhvxfocuyqu

Understanding and mitigating refresh overheads in high-density DDR4 DRAM systems

Janani Mukundan, Hillery Hunter, Kyu-hyoun Kim, Jeffrey Stuecheli, José F. Martínez
2013 Proceedings of the 40th Annual International Symposium on Computer Architecture - ISCA '13  
When looking at the refresh problem more closely, we identify in high-density DRAM systems a phenomenon that we call command queue seizure, whereby the memory controller's command queue seizes up temporarily  ...  A refresh command blocks a full rank, decreasing available parallelism in the memory subsystem significantly, thus decreasing performance.  ...  This work was supported in part by NSF Award CNS-0720773.  ... 
doi:10.1145/2485922.2485927 dblp:conf/isca/MukundanHKSM13 fatcat:ftskmc5c4jadde7meb2qkhxm2a

Understanding and mitigating refresh overheads in high-density DDR4 DRAM systems

Janani Mukundan, Hillery Hunter, Kyu-hyoun Kim, Jeffrey Stuecheli, José F. Martínez
2013 SIGARCH Computer Architecture News  
When looking at the refresh problem more closely, we identify in high-density DRAM systems a phenomenon that we call command queue seizure, whereby the memory controller's command queue seizes up temporarily  ...  A refresh command blocks a full rank, decreasing available parallelism in the memory subsystem significantly, thus decreasing performance.  ...  This work was supported in part by NSF Award CNS-0720773.  ... 
doi:10.1145/2508148.2485927 fatcat:bzxl4bpcija3noa67x37pphfx4

An energy-efficient and scalable eDRAM-based register file architecture for GPGPU

Naifeng Jing, Yao Shen, Yao Lu, Shrikanth Ganapathy, Zhigang Mao, Minyi Guo, Ramon Canal, Xiaoyao Liang
2013 SIGARCH Computer Architecture News  
To mitigate the impact of periodic refresh, we propose two novel refresh solutions using bank bubble and bank walk-through.  ...  This provides a unique opportunity to hide the refresh overhead. We propose two different eDRAM implementations based on 3T1D and 1T1C memory cells.  ...  We propose several optimization techniques to reduce the performance penalty incurred by refresh operations.  ... 
doi:10.1145/2508148.2485952 fatcat:nbaghtk2rvhfri6wkpah4t27ta

An energy-efficient and scalable eDRAM-based register file architecture for GPGPU

Naifeng Jing, Yao Shen, Yao Lu, Shrikanth Ganapathy, Zhigang Mao, Minyi Guo, Ramon Canal, Xiaoyao Liang
2013 Proceedings of the 40th Annual International Symposium on Computer Architecture - ISCA '13  
To mitigate the impact of periodic refresh, we propose two novel refresh solutions using bank bubble and bank walk-through.  ...  This provides a unique opportunity to hide the refresh overhead. We propose two different eDRAM implementations based on 3T1D and 1T1C memory cells.  ...  We propose several optimization techniques to reduce the performance penalty incurred by refresh operations.  ... 
doi:10.1145/2485922.2485952 dblp:conf/isca/JingSLGMGCL13 fatcat:niswlskhwbgxvc27zdnc5bnq54

Understanding and Improving the Latency of DRAM-Based Memory Systems [article]

Kevin K. Chang
2017 arXiv   pre-print
In this dissertation, we identify three main problems that contribute significantly to long latency of DRAM accesses. To address these problems, we present a series of new techniques.  ...  Therefore, long DRAM latency continues to be a critical performance bottleneck in modern systems.  ...  Summary We introduced two new complementary techniques, DARP (Dynamic Access Refresh Parallelization) and SARP (Subarray Access Refresh Parallelization), to mitigate the DRAM refresh penalty by enhancing  ... 
arXiv:1712.08304v1 fatcat:6y2nr2eowvb5fhr7km7azmkioe

Restore truncation for performance improvement in future DRAM systems

Xianwei Zhang, Youtao Zhang, Bruce R. Childers, Jun Yang
2016 2016 IEEE International Symposium on High Performance Computer Architecture (HPCA)  
After an access, RT restores a bit cell's voltage only to the level required to persist data to the next scheduled refresh rather than to the default full voltage.  ...  Scaling DRAM below 20nm has become a major challenge due to intrinsic limitations in the structure of a bit cell.  ...  Because the third choice is compatible with the need for high chip density and yield, we adopt it in this paper. We relax restore timing and strive to mitigate associated performance degradation.  ... 
doi:10.1109/hpca.2016.7446093 dblp:conf/hpca/ZhangZCY16 fatcat:dckypmnbl5cwrnomkxpzuisdei
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