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Towards a verification technique for large synchronous circuits [chapter]

Prabhat Jain, Prabhakar Kudva, Ganesh Gopalakrishnan
1993 Lecture Notes in Computer Science  
A new technique to encode the state and input constraints as parametric Boolean expressions over the state and input variables is used to make our symbolic simulation based verification approach efficient  ...  This technique of using parametric Boolean expressions vastly reduces the number of symbolic simulation vectors and the time for verification.  ...  One of the main observations is that the parametric Boolean expressions can be used in variety of ways for efficient symbolic simulation based verification of large synchronous circuits.  ... 
doi:10.1007/3-540-56496-9_10 fatcat:mgmiuxnuhbdadnztml3bsfq2pq

Formal verification using parametric representations of Boolean constraints

Mark D. Aagaard, Robert B. Jones, Carl-Johan H. Serger
1999 Proceedings of the 36th ACM/IEEE conference on Design automation conference - DAC '99  
We describe the use of parametric representations of Boolean predicates to encode data-space constraints and significantly extend the capacity of formal verification.  ...  The constraints are used to decompose verifications by sets of case splits and to restrict verifications by validity conditions. Our technique is applicable to any symbolic simulator.  ...  procedures to justify the floating-point case splits, and Mike Jones for his comments on a draft of the paper.  ... 
doi:10.1145/309847.309968 dblp:conf/dac/AagaardJS99 fatcat:szvd5ykjgzd3nn4gp4xejvhlbu

Algebraic Verification Method for SEREs Properties via Groebner Bases Approaches

Ning Zhou, Jinzhao Wu, Xinyan Gao
2013 Journal of Applied Mathematics  
The method is essentially based on both Groebner bases approaches and symbolic simulation.  ...  The computational experience result in this work shows that the algebraic approach is a quite competitive checking method and will be a useful supplement to the existent verification methods based on simulation  ...  Acknowledgments The project is supported by the National Natural Science Foundation of China under Grant no. 60973147, the Natural Science Foundation of Guangxi under Grant no. 2011GXNSFA018154, the Science  ... 
doi:10.1155/2013/272781 fatcat:upczmfpa5jbuxp47pzxdnkruwu

Use of Formal Verification at Centaur Technology [chapter]

Warren A. Hunt, Sol Swords, Jared Davis, Anna Slobodova
2010 Design and Verification of Microprocessor Systems for High-Assurance Applications  
The HDL simulator is used both to run concrete test cases and to extract symbolic representations of the circuit logic of blocks of interest.  ...  We have developed a formal-methods-based hardware verification toolflow to help ensure the correctness of our X86-compatible microprocessors.  ...  We would also like to thank Bob Boyer for development of much of the technology behind EMOD and the ACL2 BDD package, Terry Parks for developing a very detailed floating-point addition specification, and  ... 
doi:10.1007/978-1-4419-1539-9_3 fatcat:qczrzp6ah5a5lmq75hllk6oymq

Abstraction by Symbolic Indexing Transformations [chapter]

Thomas F. Melham, Robert B. Jones
2002 Lecture Notes in Computer Science  
We present logical machinery and efficient algorithms that provide a much simpler interface to symbolic indexing for the STE user.  ...  Use of this technique has been somewhat limited in practice because of its complexity.  ...  We thank the anonymous referees for their careful reading of the paper and very helpful comments. John Harrison and Ashish Darbari also provided useful remarks on notation.  ... 
doi:10.1007/3-540-36126-x_1 fatcat:4fyl33brirh5dbsbu6yp3e3slu

An industrially effective environment for formal hardware verification

C.-J.H. Seger, R.B. Jones, J.W. O'Leary, T. Melham, M.D. Aagaard, C. Barrett, D. Syme
2005 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
The design philosophy behind Forte is presented and the elements of the verification methodology that make it effective in practice are also described.  ...  Forte has proven to be effective in large-scale industrial trials and combines an efficient linear-time logic model-checking algorithm, namely the symbolic trajectory evaluation (STE), with lightweight  ...  The authors are particularly grateful to the users of Forte at Intel and to the Intel design teams who supplied case studies for their own example verifications.  ... 
doi:10.1109/tcad.2005.850814 fatcat:rxashd5osrhcjky5mgq2jsodk4

Introduction to generalized symbolic trajectory evaluation

Jin Yang, C.-J.H. Seger
2003 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
Hu and the reviewers for reading the paper and providing many valuable suggestions.  ...  Seger Abstract-Symbolic trajectory evaluation (STE) is a lattice-based model checking technology that uses a form of symbolic simulation.  ...  Symbolic constants are introduced in an STE assertion for two purposes,1) to encode an arbitrary boolean constraints among a set of circuit nodes in a parametric form [3] and 2) to encode all possible  ... 
doi:10.1109/tvlsi.2003.812320 fatcat:wsx4z7cmyzgxpjmgwjaruniejy

A SAT-based algorithm for reparameterization in symbolic simulation

Pankaj Chauhan, Edmund M. Clarke, Daniel Kroening
2004 Proceedings of the 41st annual conference on Design automation - DAC '04  
Parametric representations used for symbolic simulation of circuits usually use BDDs.  ...  Efficient SAT solvers have been applied successfully for many verification problems.  ...  Therefore, symbolic simulators that use non-canonical Boolean expressions can go much deeper. Thus, we seek to compute h i when the functions are given as Boolean expressions.  ... 
doi:10.1145/996566.996711 dblp:conf/dac/ChauhanCK04 fatcat:pkcmbs2j3fg4lmshzvd5yb54ve

Symbolic Model-Checking Using ITS-Tools [chapter]

Yann Thierry-Mieg
2015 Lecture Notes in Computer Science  
We present verification toolset ITS-tools, featuring a symbolic modelchecking back-end engine based on hierarchical set decision diagrams (SDD) that supports reachability, CTL and LTL model-checking and  ...  a user-friendly eclipse based front-end.  ...  The ITS-tools is the result of many years of collaborative development with both colleagues and students at LIP6, without whom this tool presentation would not be possible.  ... 
doi:10.1007/978-3-662-46681-0_20 fatcat:wuraebux5rguvm5k2gxdb2zpg4

Assume-guarantee validation for STE properties within an SVA environment

Zurab Khasidashvili, Gavriel Gavrielov, Tom Melham
2009 2009 Formal Methods in Computer-Aided Design  
Symbolic Trajectory Evaluation is an industrialstrength verification method, based on symbolic simulation and abstraction, that has been highly successful in data path verification, especially microprocessor  ...  These are then used as checkers in dynamic validation of the hardware environment within which blocks verified by Symbolic Trajectory Evaluation operate.  ...  Shachar Finkelstein was largely responsible for deploying STE2SVA and provided us with benchmark data. Roope Kaivola kindly provided helpful comments on a draft of the paper.  ... 
doi:10.1109/fmcad.2009.5351133 dblp:conf/fmcad/KhasidashviliGM09 fatcat:wbtdhelzandjdefwqdlorbimvq

Symbolic Model Checking for Asynchronous Boolean Programs [chapter]

Byron Cook, Daniel Kroening, Natasha Sharygina
2005 Lecture Notes in Computer Science  
We address the first type of non-determinism with a form of symbolic execution and fix-point detection.  ...  We address the second source of non-determinism using a symbolic and dynamic partial-order reduction, which is implemented inside the SAT-solver's case-splitting algorithm.  ...  We have presented a SAT-based model checking approach that can be used to efficiently reason about the safety of Boolean programs with both symbolic data and multiple threads.  ... 
doi:10.1007/11537328_9 fatcat:qsi2kmk645bdbahzmh3i43uuue

Groebner Bases Based Verification Solution for SystemVerilog Concurrent Assertions

Ning Zhou, Xinyan Gao, Jinzhao Wu, Jianchao Wei, Dakui Li
2014 Journal of Applied Mathematics  
We present an algorithm framework based on the algebraic representations using Groebner bases for concurrent SVAs checking.  ...  We introduce an approach exploiting the power of polynomial ring algebra to perform SystemVerilog assertion verification over digital circuit systems.  ...  Acknowledgments The project is supported by the National Natural Science Foundation of China under Grant no. 11371003, the Natural Science Foundation of Guangxi under Grants nos. 2011GXNSFA018154, 2012GXNSFGA060003  ... 
doi:10.1155/2014/194574 fatcat:sypgbdfdfbhoblte6rfz7vh7ky

GSTE through a case study

Jin Yang, Amit Goel
2002 Computer-Aided Design (ICCAD), IEEE International Conference on  
It also extends the symbolic quaternary model used by STE to support seamless model refinement for efficiency and accuracy trade-off in GSTE model checking.  ...  Generalized Symbolic Trajectory Evaluation (GSTE) [17, 18, 19 ] is a very significant extension of STE that has the power to verify all ω-regular properties but at the same time preserves the benefits  ...  Acknowledgment We would like to thank Brian Moore, Carl Seger, Rajnish Ghughal, Andreas Tiemeyer and Alan Hu for reading the paper and providing many useful suggestions.  ... 
doi:10.1145/774572.774651 dblp:conf/iccad/YangG02 fatcat:qszmvdoa5fdpxm6svziosansi4

Relational STE and theorem proving for formal verification of industrial circuit designs

John O'Leary, Roope Kaivola, Tom Melham
2013 2013 Formal Methods in Computer-Aided Design  
We illustrate the effectiveness of this combination of technologies by describing a general framework, accessible to non-experts, that is widely used for verification and regression validation of integer  ...  This paper describes an approach to verification by symbolic simulation, called Relational STE, that raises verification properties to the purely logical level suitable for compositional reasoning in a  ...  Separating out the constraints cin can also allow some them to be injected into the symbolic simulation using parametric substitution [26] , futher improving efficiency.  ... 
doi:10.1109/fmcad.2013.6679397 fatcat:76aebjztijc5tmbhzzixkjtuwu

Building Circuits from Relations [chapter]

James H. Kukula, Thomas R. Shiple
2000 Lecture Notes in Computer Science  
The resulting circuit C can be used for further analysis, e.g. symbolic simulation, or to reformat a circuit as a logic optimization tactic.  ...  The structure of the circuit is isomorphic to that of the BDD for T , and hence is as compact as the BDD.  ...  The constraints may also improve the efficiency of state exploration techniques such as symbolic simulation by reducing BDD sizes [1] .  ... 
doi:10.1007/10722167_12 fatcat:mlqitban6jd4dayufhnssp2k64
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