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Efficient microarchitecture policies for accurately adapting to power constraints

Juan M. Cebrian, Juan L. Aragon, Jose M. Garcia, Pavlos Petoumenos, Stefanos Kaxiras
2009 2009 IEEE International Symposium on Parallel & Distributed Processing  
In this paper we propose the use of microarchitectural techniques to accurately match a power constraint while maximizing the energy efficiency of the processor.  ...  We propose a two-level approach where DVFS acts as a coarse-grained technique to lower the average power while microarchitectural techniques remove all the power spikes efficiently.  ...  We need processors able to accurately adapt to a given power budget in real time in an energy-efficient way.  ... 
doi:10.1109/ipdps.2009.5161022 dblp:conf/ipps/CebrianAGPK09 fatcat:ydn7r545sja4jpkcl2cbzdyccu

Managing power constraints in a single-core scenario through power tokens

Juan M. Cebrián, Daniel Sánchez, Juan L. Aragón, Stefanos Kaxiras
2013 Journal of Supercomputing  
In this paper, we propose the use of microarchitectural techniques to accurately match a power constraint while maximizing the energy-efficiency of the processor.  ...  Experimental results show that the use of power-saving microarchitectural techniques in conjunction with DVFS is up to six  ...  It can be observed that all microarchitectural techniques are far more accurate than DVFS when adapting to the imposed power budget.  ... 
doi:10.1007/s11227-013-1044-2 fatcat:5c2weo65yvgvvibp3rltisahvu

Power Token Balancing: Adapting CMPs to Power Constraints for Parallel Multithreaded Workloads

Juan M. Cebri´n, Juan L. Aragón, Stefanos Kaxiras
2011 2011 IEEE International Parallel & Distributed Processing Symposium  
In order to solve this problem we propose a novel mechanism, Power Token Balancing (PTB), aimed at accurately matching an external power constraint by balancing the power consumed among the different cores  ...  Results show that PTB matches more accurately a predefined power budget (total energy consumed over the budget is reduced to 8% for a 16-core CMP) than DVFS with only a 3% energy increase.  ...  We also want to thank Varadan Savulimedu for his support on estimating the power consumption and interconnection delay of the PTB mechanism.  ... 
doi:10.1109/ipdps.2011.49 dblp:conf/ipps/CebrianAK11 fatcat:46ksfhccuzbunohrcgpklk7zg4

Reducing wearout in embedded processors using proactive fine-grain dynamic runtime adaptation

Fabian Oboril, Mehdi B. Tahoori
2012 2012 17TH IEEE EUROPEAN TEST SYMPOSIUM (ETS)  
The experimental results presented in this work show lifetime improvements between 63% up to 5x, while the required performance as well as power and temperature constraints are maintained.  ...  To extend lifetime, reduce power and heat, while maintaining the required performance we propose a dynamic runtime adaptation approach, which is based on runtime monitoring of temperature, performance,  ...  Therefore a suitable microarchitectural framework containing accurate models for power, temperature and aging is necessary.  ... 
doi:10.1109/ets.2012.6233012 dblp:conf/ets/OborilT12 fatcat:lcnbchbssrhmrkqypq4sysnyoe

Joint exploration of architectural and physical design spaces with thermal consideration

Yen-Wei Wu, Chia-Lin Yang, Ping-Hung Yuh, Yao-Wen Chang
2005 Proceedings of the 2005 international symposium on Low power electronics and design - ISLPED '05  
Heat is a main concern for processors in deep sub-micron technologies. The chip temperature is affected by both the power consumption of processor components and the chip layout.  ...  Therefore, for thermal-aware design it is crucial to consider the thermal effects of different floorplans during micro-architectural design space exploration.  ...  Adaptive + Heuristic for Each Configuration. Table 1 : 1 32 Different Microarchitectural Configura- tions.  ... 
doi:10.1145/1077603.1077636 dblp:conf/islped/WuYYC05 fatcat:aq5eijo47fanhi5n6cjxqgwvtu

Joint exploration of architectural and physical design spaces with thermal consideration

Yen-Wei Wu, Chia-Lin Yang, Ping-Hung Yuh, Yao-Wen Chang
2005 ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005.  
Heat is a main concern for processors in deep sub-micron technologies. The chip temperature is affected by both the power consumption of processor components and the chip layout.  ...  Therefore, for thermal-aware design it is crucial to consider the thermal effects of different floorplans during micro-architectural design space exploration.  ...  Adaptive + Heuristic for Each Configuration. Table 1 : 1 32 Different Microarchitectural Configura- tions.  ... 
doi:10.1109/lpe.2005.195500 fatcat:jqtmk57slzfyxndombhqcp6to4

Application Specific Instruction Set Processor for Adaptive Video Motion Estimation

S. Momcilovic, T. Dias, N. Roma, L. Sousa
2006 9th EUROMICRO Conference on Digital System Design (DSD'06)  
Due to its low-power nature, this architecture is specially adequate to develop motion estimators for portable, mobile and battery supplied devices.  ...  A cycle-based accurate simulator was also developed for the proposed ASIP and fast and data-adaptive search algorithms have been implemented, namely, the four-step search and the motion vector field adaptive  ...  Microarchitecture The proposed ISA is supported by a specially designed microarchitecture, following strict power and area driven policies to support its implementation in portable and mobile platforms  ... 
doi:10.1109/dsd.2006.25 dblp:conf/dsd/MomcilovicDRS06 fatcat:scsbfzl3obgejjs2hiuh5posfa

Power balanced pipelines

John Sartori, Ben Ahrens, Rakesh Kumar
2012 IEEE International Symposium on High-Performance Comp Architecture  
A specific implementation of the concept uses cycle time stealing [19] to deliberately redistribute cycle time from low-power pipeline stages to power-hungry stages, relaxing their timing constraints and  ...  In this paper, rather than balancing processor pipelines for delay, we propose the concept of power balanced pipelines -i.e., processor pipelines in which different delays are assigned to different microarchitectural  ...  We would like to thank Janak Patel and the anonymous reviewers for providing feedback that helped improve this work.  ... 
doi:10.1109/hpca.2012.6169032 dblp:conf/hpca/SartoriAK12 fatcat:loa744z7hve2pfb6koygx23dse

Microprocessor Optimizations for the Internet of Things: A Survey

Tosiron Adegbija, Anita Rogacs, Chandrakant Patel, Ann Gordon-Ross
2018 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
This paper explores IoT applications' execution characteristics from a microarchitectural perspective and the microarchitectural characteristics that will enable efficient and effective edge computing.  ...  We then survey and discuss potential microarchitectural optimizations and computing paradigms that will enable the design of right-provisioned microprocessors that are efficient, configurable, extensible  ...  While most of these techniques can also be employed in IoT devices, one critical requirement for IoT devices is the need to have runtime configurable hardware security policies that can adapt to varying  ... 
doi:10.1109/tcad.2017.2717782 fatcat:nnf5vx3sd5dq3ic2qjexvi6euq

Adaptive Motion Estimation Processor for Autonomous Video Devices

T. Dias, S. Momcilovic, N. Roma, L. Sousa
2007 EURASIP Journal on Embedded Systems  
Due to its low-power nature, this architecture is highly suitable to develop motion estimators for portable, mobile, and battery-supplied devices.  ...  Experimental results show that the proposed architecture is able to estimate motion vectors in real time for QCIF and CIF video sequences with a very low-power consumption.  ...  Micro architecture The proposed ISA is supported by a specially designed microarchitecture, following strict power and area driven policies to support its implementation in portable and mobile platforms  ... 
doi:10.1155/2007/57234 fatcat:agk4ekthfrbmxkdczt2tzatdcu

Adaptive Motion Estimation Processor for Autonomous Video Devices

T Dias, S Momcilovic, N Roma, L Sousa
2007 EURASIP Journal on Embedded Systems  
Due to its low-power nature, this architecture is highly suitable to develop motion estimators for portable, mobile, and battery-supplied devices.  ...  Experimental results show that the proposed architecture is able to estimate motion vectors in real time for QCIF and CIF video sequences with a very low-power consumption.  ...  Micro architecture The proposed ISA is supported by a specially designed microarchitecture, following strict power and area driven policies to support its implementation in portable and mobile platforms  ... 
doi:10.1186/1687-3963-2007-057234 fatcat:ni654uhp3rekvkzskmgzfcjoja

An Analysis of Efficient Multi-Core Global Power Management Policies: Maximizing Performance for a Given Power Budget

Canturk Isci, Alper Buyuktosunoglu, Chen-yong Cher, Pradip Bose, Margaret Martonosi
2006 Microarchitecture (MICRO), Proceedings of the Annual International Symposium on  
Chip-level power and thermal implications will continue to rule as one of the primary design constraints and performance limiters.  ...  We evaluate several different policies for global multi-core power management. In this analysis, we consider various different objectives such as prioritization and optimized throughput.  ...  Adaptive responses to such phases for power-efficient computing in a uniprocessor setting have been well studied in the past (e.g. [1] ).  ... 
doi:10.1109/micro.2006.8 dblp:conf/micro/IsciBCBM06 fatcat:cpjczbndnrep7laeqk76bwtngm

Machine Learning and Manycore Systems Design: A Serendipitous Symbiosis [article]

Ryan Gary Kim, Janardhan Rao Doppa, Partha Pratim Pande, Diana Marculescu, Radu Marculescu
2017 arXiv   pre-print
Such a framework will be necessary to address the rising complexity of designing large-scale manycore systems and machine learning techniques.  ...  Tight collaboration between experts of machine learning and manycore system design is necessary to create a data-driven manycore design framework that integrates both learning and expert knowledge.  ...  Two major objectives are typically considered when designing dynamic manycore policies: Creating a policy that can adapt to changing circumstances and creating a way for the policy to accurately predict  ... 
arXiv:1712.00076v1 fatcat:rqju4xmpmjetzpbwlnr6x3gbmu

Register File Reliability Analysis Through Cycle-Accurate Thermal Emulation

José L. Ayala, Pablo G. Del Valle, David Atienza
2008 2008 International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems  
Continuous transistor scaling due to improvements in CMOS devices and manufacturing technologies is increasing processor power densities and temperatures; thus, creating challenges when trying to maintain  ...  Our results quantify the respective effects of these different factors and enable us to design a reliabilityaware register file assignment policy that consistently improves the Mean-Time-To-Failure figure  ...  be very complex because cycle-accurate MPSoC simulators [5] , [6] need to run for millions of cycles to accurately characterize the systems switching activity and behavior.  ... 
doi:10.1109/iwia.2008.7 fatcat:5t2x7s7lffcfjoku7oayrzumwe

Independent Front-end and Back-end Dynamic Voltage Scaling for a GALS Microarchitecture

Grigorios Magklis, Pedro Chaparro, Jose Gonzalez, Antonio Gonzalez
2006 ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design  
We evaluate our mechanisms for both internal and external voltage regulators, and we present optimal dynamic voltage scaling results for the proposed microarchitecture.  ...  In recent years, Globally Asynchronous Locally Synchronous (GALS) designs and dynamic voltage scaling (DVS) have emerged as some of the most popular approaches to address the ever increasing microprocessor  ...  We are more conservative and assume only 90% efficiency. Our power model accounts for power losses due to the regulator inefficiency (independently for each regulator).  ... 
doi:10.1109/lpe.2006.4271806 fatcat:mkwl3o7oqjamlermohuozpsx2q
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