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Efficient memory layout for packet classification system on multi-core architecture

Shariful Hasan Shaikot, Min Sik Kim
2012 2012 IEEE Global Communications Conference (GLOBECOM)  
Bakken for serving on my committee.  ...  I highly appreciate their time for the discussion on several occasions about my research and for providing me the relevant reading materials which really helped me to understand the insight of theories  ...  CHAPTER three EFFICIENT MEMORY LAYOUT FOR PACKET CLASSIFICATION SYSTEM In decision tree based packet classification system, packets are classified by searching in the tree data structure.  ... 
doi:10.1109/glocom.2012.6503501 dblp:conf/globecom/ShaikotK12 fatcat:xk7ua5ldpbfsxghuuzb63tvtsq

A scalable multithreaded L7-filter design for multi-core servers

Danhua Guo, Guangdeng Liao, Laxmi N. Bhuyan, Bin Liu, Jianxun Jason Ding
2008 Proceedings of the 4th ACM/IEEE Symposium on Architectures for Networking and Communications Systems - ANCS '08  
for scalable utilization on multi-core servers.  ...  Unfortunately, the proliferation of multi-core architectures has not helped fast packet processing due to: 1) the lack of efficient parallelism in legacy network programs, and 2) the non-trivial configuration  ...  Multi-Core Architecture Multi-core architecture duplicates hardware resources such as ALU, L1 cache, etc. on the same die, and hence allows multiple processes to run concurrently on different cores.  ... 
doi:10.1145/1477942.1477952 dblp:conf/ancs/GuoLBLD08 fatcat:h2l4szsvdfc7no6u5l76v2szyy

Scalable packet classification using interpreting

Haipeng Cheng, Zheng Chen, Bei Hua, Xinan Tang
2008 Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming - PPoPP '08  
This paper presents a classification algorithm that can be efficiently implemented on a multi-core architecture with or without cache.  ...  By effectively using the cache system, the algorithm also runs faster than the previous fastest RFC on the Core 2 Duo architecture.  ...  Acknowledgements We would like to thank the anonymous reviewers for their valuable comments, and Julian Horn (Intel) for proofreading our paper.  ... 
doi:10.1145/1345206.1345214 dblp:conf/ppopp/ChengCHT08 fatcat:5zfa6z77cnhebh5v2z7uyrsmim

The limits of architectural abstraction in network function virtualization

Balazs Nemeth, Xavier Simonart, Neal Oliver, Wim Lamotte
2015 2015 IFIP/IEEE International Symposium on Integrated Network Management (IM)  
For this reason, emerging NFV standards will confront the challenge of exposing certain platform architectural parameters to enable services to be orchestrated in an effective manner.  ...  However, existing CPU, memory, and network interface architectures cause network service performance to be sensitive both to the implementation of individual network functions, but also to their placement  ...  Even in this case, QoS parameters, classification implementation (mapping from packet to a tuple) and core layout (e.g.  ... 
doi:10.1109/inm.2015.7140348 dblp:conf/im/NemethSOL15 fatcat:wsdudu4qlze3bcgamqb5zwhazm

On-chip communication architecture for OC-768 network processors

Faraydon Karim, Anh Nguyen, Sujit Dey, Ramesh Rao
2001 Proceedings of the 38th conference on Design automation - DAC '01  
Such ultra high-speed processing, involving complex memory-intensive tasks, can only be achieved by multi-CPU distributed memory systems, using very high performance on-chip communication architectures  ...  At the same time, there is a growing need for complex tasks, like packet classification and differentiated services, to be performed by network processors.  ...  Consequently, next-generation network processors will have to be based on multi-processor/distributed memory architectures.  ... 
doi:10.1145/378239.379047 dblp:conf/dac/KarimNDR01 fatcat:awh4ohtxbnckdfgefo2urziepe

On Multi–gigabit Packet Capturing with Multi–core Commodity Hardware [chapter]

Nicola Bonelli, Andrea Di Pietro, Stefano Giordano, Gregorio Procissi
2012 Lecture Notes in Computer Science  
Therefore we designed a novel packet capturing engine, named PFQ, that allows efficient capturing and in-kernel aggregation, as well as connection-aware load balancing.  ...  Such an engine is based on a novel lockless queue and allows parallel packet capturing to let the user-space application arbitrarily define its degree of parallelism.  ...  Acknowledgments The authors wish to thanks Luca Deri for his support towards this research.  ... 
doi:10.1007/978-3-642-28537-0_7 fatcat:tpnt2fkarndnjbr3oizgzpklaq

Enhancing the performance of the aggregated bit vector algorithm in network packet classification using GPU

Mahdi Abbasi, Razieh Tahouri, Milad Rafiee
2019 PeerJ Computer Science  
The aggregated bit vector is a highly parallelizable packet classification algorithm. In this work, first we present a parallel kernel for running this algorithm on GPUs.  ...  Packet classification is a computationally intensive, highly parallelizable task in many advanced network systems like high-speed routers and firewalls that enable different functionalities through discriminating  ...  In contrast, the reduced dependence of tuple space and decomposition algorithms on data and control makes them more appropriate for the parallelism on multi-core and many-core systems.  ... 
doi:10.7717/peerj-cs.185 pmid:33816838 pmcid:PMC7924471 fatcat:6rb3wqxafjghbpktcuzodp3ime

A pipelined memory architecture for high throughput network processors

Timothy Sherwood, George Varghese, Brad Calder
2003 Proceedings of the 30th annual international symposium on Computer architecture - ISCA '03  
In this paper we focus on the design of a programmable architecture for backbone routers, based on the manipulation of wide irregular memory words, that can provide a feasible design alternative to custom  ...  Through this co-exploration, we show that a programmable architecture can efficiently exploit behavior inherent to most common network algorithms to keep up with next generation network speeds.  ...  Acknowledgments We would like to thank Jeremy Lau, Kristina Sherwood, and our anonymous reviewers for providing useful comments on this paper, and Nathan Tuck for his feedback on both the writing and analytical  ... 
doi:10.1145/859618.859652 fatcat:gqbkgwedrjd6lhfdut3wyaqhre

A pipelined memory architecture for high throughput network processors

Timothy Sherwood, George Varghese, Brad Calder
2003 SIGARCH Computer Architecture News  
In this paper we focus on the design of a programmable architecture for backbone routers, based on the manipulation of wide irregular memory words, that can provide a feasible design alternative to custom  ...  Through this co-exploration, we show that a programmable architecture can efficiently exploit behavior inherent to most common network algorithms to keep up with next generation network speeds.  ...  Acknowledgments We would like to thank Jeremy Lau, Kristina Sherwood, and our anonymous reviewers for providing useful comments on this paper, and Nathan Tuck for his feedback on both the writing and analytical  ... 
doi:10.1145/871656.859652 fatcat:bjx7au4rrvdb7fymgiedanp25m

A pipelined memory architecture for high throughput network processors

Timothy Sherwood, George Varghese, Brad Calder
2003 Proceedings of the 30th annual international symposium on Computer architecture - ISCA '03  
In this paper we focus on the design of a programmable architecture for backbone routers, based on the manipulation of wide irregular memory words, that can provide a feasible design alternative to custom  ...  Through this co-exploration, we show that a programmable architecture can efficiently exploit behavior inherent to most common network algorithms to keep up with next generation network speeds.  ...  Acknowledgments We would like to thank Jeremy Lau, Kristina Sherwood, and our anonymous reviewers for providing useful comments on this paper, and Nathan Tuck for his feedback on both the writing and analytical  ... 
doi:10.1145/859651.859652 fatcat:s6t7kqxhmnggjisfueguwgfyke

An adaptive hash-based multilayer scheduler for L7-filter on a highly threaded hierarchical multi-core server

Danhua Guo, Guangdeng Liao, Laxmi N. Bhuyan, Bin Liu
2009 Proceedings of the 5th ACM/IEEE Symposium on Architectures for Networking and Communications Systems - ANCS '09  
Ubiquitous multi-core-based web servers and edge routers are increasingly popular in deploying computationally intensive Deep Packet Inspection (DPI) programs.  ...  Previous work has shown the benefits of connection locality-based scheduling on multi-core servers to improve L7-filter performance.  ...  The authors would like to thank anonymous reviewers for their valuable comments. We also thank Intel for providing the Sun Niagara 2 based web server.  ... 
doi:10.1145/1882486.1882497 dblp:conf/ancs/GuoLBL09 fatcat:dcf6ok7sgjeabibrudgbkkj36i

PR03: a hybrid NPU architecture

I. Papaefstathiou, S. Perissakis, T.G. Orphanoudakis, N.A. Nikolaou, N.A. Zervos, G. Konstantoulakis, D.N. Pnevmatikatos, K. Vlachos
2004 IEEE Micro  
PRO3 architecture The initial NPU approach, focused on high-speed switching and routing systems, usually results in multi-chip solutions comprised of dedicated classifiers, traffic managers, and switch  ...  His research interests include architectures for network processors and specific-purpose networking systems.  ... 
doi:10.1109/mm.2004.55 fatcat:iq6i6zmwuje3nenjszlsutimde

Zooming in on Network-on-Chip Architectures [chapter]

Israel Cidon
2010 Lecture Notes in Computer Science  
We present a new classification of chip architectures into three categories with different requirements from their NoCs.  ...  role, and new network architectures are in demand.  ...  ACKNOWLEDGMENTS The authors thank Evgeny Bolotin, Roman Gindin, Ran Ginosar, Zvika Guz, Avinoam Kolodny, Ehud Shavit, and Isask'har Walter for helpful discussions and for many of the initial results presented  ... 
doi:10.1007/978-3-642-11476-2_1 fatcat:gsipffo6v5covck6jqsk2jeimy

Ruler

Tomas Hruby, Kees van Reeuwijk, Herbert Bos
2007 Proceedings of the 3rd ACM/IEEE Symposium on Architecture for networking and communications systems - ANCS '07  
In this paper, we present one such programming model: Ruler, a flexible high-level language for deep packet inspection (DPI) and packet rewriting that is easy to learn, platform independent and lets the  ...  Software development on such architectures is expensive.  ...  Acknowledgments We would like to thank Lennert Buytenhek for his invaluable help during development of the IXP code and Willem de Bruin for commenting on earlier versions of this paper.  ... 
doi:10.1145/1323548.1323550 dblp:conf/ancs/HrubyRB07 fatcat:zqwhok7lzjh4tocsgylf6srhsu

Design and implementation of a framework for creating portable and efficient packet-processing applications

Olivier Morandi, Fulvio Risso, Silvio Valenti, Paolo Veglia
2008 Proceedings of the 7th ACM international conference on Embedded software - EMSOFT '08  
Our implementation supports three different target architectures: one with a general purpose processor (Intel x86), one with a multi-core network processor (Cavium Octeon) and one with a systolic-array  ...  It is a common belief that using a virtual machine for portable executions of data-plane packet-processing applications would introduce too many penalties in terms of performance, because of the assumed  ...  ACKNOWLEDGEMENTS The authors wish to thank Marco Bergero and Pierluigi Rolando for the contribution they have given respectively in the development of the NetVM runtime environment and of the optimization  ... 
doi:10.1145/1450058.1450091 dblp:conf/emsoft/MorandiRVV08 fatcat:jleeuytcufafvllqfdkqbu7qfy
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