Filters








118 Hits in 3.7 sec

A 110-K transistor 25-MPixels/s configurable image transform processor unit

S. Molloy, R. Jain
1998 IEEE Journal of Solid-State Circuits  
By emulating the signal flow of the algorithms in hardware, rather than software, complexity is reduced by an order of magnitude compared with current software programmable video signal processors, while  ...  The processor has been fabricated in 1.2-m CMOS and has been successfully used to execute the discrete cosine transform/inverse discrete cosine transform (DCT/IDCT), subband coding, vector quantization  ...  These macro-instructions are hardwired in the configurable architecture, allowing the full parallelism within the macro-instruction to be exploited.  ... 
doi:10.1109/4.654940 fatcat:5zmy3eykinfbnpyktkraucgntu

Configware and morphware going mainstream

Jürgen Becker, Reiner Hartenstein
2003 Journal of systems architecture  
The paper addresses a broad readership in information technology, computer science and related areas, and gives an introduction to fine grain and coarse grain morphware, reconfigurable computing, and its  ...  memory bottleneck not only by using accelerators, but also by innovative computing architectures, or even by breaking the dominance of the von Neumann machine paradigm is a promising goal of new trends in  ...  On hardwired DPU array basis the BWRC [34] has trumped a ''chip in a day'' design methodology by direct mapping of algorithms onto high-level, pre-characterized macros wired together from a Simulink  ... 
doi:10.1016/s1383-7621(03)00073-0 fatcat:ebvbvahp35cdfmymcru6e73yrq

PGPG: An Automatic Generator of Pipeline Design for Programmable GRAPE Systems

Tsuyoshi Hamada, Toshiyuki Fukushige, Junichiro Makino
2005 Nippon Tenmon Gakkai obun kenkyu hokoku  
For real applications such as the pipeline for gravitational interaction, the pipeline processor generated by PGPG achieved the performance similar to that of hand-written code.  ...  The PGPG language is a simple language, specialized to the description of pipeline processors. Thus, the design of pipeline processor in PGPG language is much easier than the traditional design.  ...  So it is not inconceivable to design a fully pipelined, hardwired processor dedicated to the calculation of gravitational interaction.  ... 
doi:10.1093/pasj/57.5.799 fatcat:r47gdrll5fcdfm7bee3bvjlqqm

ASAM: Automatic Architecture Synthesis and Application Mapping

Lech Jozwiak, Menno Lindwer, Rosilde Corvino, Paolo Meloni, Laura Micconi, Jan Madsen, Erkan Diken, Deepak Gangadharan, Roel Jordans, Sebastiano Pomata, Paul Pop, Giuseppe Tuveri (+1 others)
2012 2012 15th Euromicro Conference on Digital System Design  
Finally, it introduces and briefly discusses the design-flow and its main stages proposed by the ASAM project consortium to enable an effective and efficient solution of these problems.  ...  Abstract -This paper focuses on mastering the automatic architecture synthesis and application mapping for heterogeneous massively-parallel MPSoCs based on customizable applicationspecific instruction-set processors  ...  The original application code is modeled for the SL DSE, as a task graph (TG): the code is partitioned into tasks (T) for extracting the task level and inter-task (pipeline) parallelism.  ... 
doi:10.1109/dsd.2012.28 dblp:conf/dsd/JozwiakLCMMMDGJPPTR12 fatcat:et5s2vcnhzbfrae2jufsqzq4gy

A high-performance low risc machine for logic programming

J.W Mills
1989 The Journal of Logic Programming  
RISC code should execute in the range of 200,000 to 700,000 LIPS.  ...  Hand-optimized RISC code is four times the size of corresponding WAM code; macro-expanded RISC code is seven times larger. a 1. INTRODUCIION David H. D.  ...  The LOW RISC Processor. The LOW RISC processor shown in Figure 2 is a Harvard bus machine [19] . The three pipelined arithmetic/logic units (ALUs) operate in parallel.  ... 
doi:10.1016/0743-1066(89)90035-6 fatcat:fze6mjuorfhc5eynqoyugoqsxm

HSP16: A Hardware Simulator for Pesona 16

Khairulmizam Samsudin, Abdul Rahman Ramli, Ismail Mat Yusoff
2002 Jurnal Teknologi  
Hardware Simulator for Pesona 16 (HSP16) is a simulated environment of the Pesona-16 microprocessor for execution of the host-code to enable parallel co-design and co-verification.  ...  The author, Khairulmizam Samsudin is currently a tutor in the Department of Computer and Communication Systems, UPM.  ...  However to emulate R0 and R1 registers that is hardwired to zero and one respectively [4] , the general registers must be accessed through a predetermined interface [15] .  ... 
doi:10.11113/jt.v36.577 fatcat:xlefqskg5jam5f7dv436uiga5e

ASAM: Automatic architecture synthesis and application mapping

Lech Jozwiak, Menno Lindwer, Rosilde Corvino, Paolo Meloni, Laura Micconi, Jan Madsen, Erkan Diken, Deepak Gangadharan, Roel Jordans, Sebastiano Pomata, Paul Pop, Giuseppe Tuveri (+2 others)
2013 Microprocessors and microsystems  
shorter time to market than the hardwired ASICs.  ...  It presents an overview of the research being currently performed in the scope of the European project ASAM of the ARTEMIS program.  ...  Acknowledgements The research reported in this paper has been performed in the scope of the ASAM project of the European ARTEMIS Research Program and has been partly supported by the ARTEMIS Joint Undertaking  ... 
doi:10.1016/j.micpro.2013.08.006 fatcat:tztiewd7vzfc5jtki2tcwursca

A retrospective on the Dorado, a high-performance personal computer

Kenneth A. Pier
1983 Proceedings of the 10th annual international symposium on Computer architecture - ISCA '83  
In late 1975, members of the Xerox Palo Alto Research Center embarked on the specification of a high·performance successor to the Alto personal minicomputer, in use since 1973.  ...  The paper concludes with some speculations on what the project might have done differently and what might be done differently today instead of in the late 1970s.  ...  The Dorado is designed for efficient execution of multiple languages that are compiled into a stream of byte codes [24] ; this execution is called emulation.  ... 
doi:10.1145/800046.801663 dblp:conf/isca/Pier83 fatcat:dznfc3ulqvdgzgw6fyjhe76elq

A formal concurrency model based architecture description language for synthesis of software development tools

Wei Qin, Subramanian Rajagopalan, Sharad Malik
2004 Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools - LCTES '04  
Rapidly increasing design and manufacturing non-recurring engineering (NRE) costs are prompting a shift in electronic design from hardwired application specific integrated circuits (ASICs) to the use of  ...  However, in order to minimize the power and performance overhead of such processors, we are seeing the introduction of domain or application specific processors such as network and communication processors  ...  While several attempts have been made to develop efficient register allocators for such processors, very few are retargetable, efficient and easy to use.  ... 
doi:10.1145/997163.997171 dblp:conf/lctrts/QinRM04 fatcat:m6ii7un4ifexthibil44cqwa7e

Hardware/Software Codesign of Processors: Concepts and Examples [chapter]

John Hennessy, Mark Cheinrich
1996 Hardware/Software Co-Design  
a macro-pipeline.  ...  The next stage of refinement replaces the high-level model of the protocol processor with a simulator thread that emulates the actual compiled protocol code and produces accurate delays.  ... 
doi:10.1007/978-94-009-0187-2_2 fatcat:gsp2pzu5hbbmhlthp4z66mwpka

Compiler generation from structural architecture descriptions

Florian Brandner, Dietmar Ebner, Andreas Krall
2007 Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems - CASES '07  
Experimental results show that the automatically derived code generator is competitive in comparison to a handcrafted compiler backend.  ...  At the same time, application specific instruction-set processors (ASIPs) are used to fine-tune hardware platforms to the intended application, demanding the availability of retargetable components throughout  ...  A phase called macro expansion transforms the IR into operations of the target processor.  ... 
doi:10.1145/1289881.1289886 dblp:conf/cases/BrandnerEK07 fatcat:jhuo57km2jhkvovguo7ks7xuq4

Run-time support for dynamically reconfigurable computing systems

Martyn Edwards, Peter Green
2003 Journal of systems architecture  
The main theme beyond this new technology is to integrate the performance benefits of application specific integrated circuits with the hardware flexibility of programmable processors in a single chip.  ...  The reconfigurable computing devices like field programmable gate arrays have already been playing a vital role in the enhancement of the existing technology but still reconfigurable computing is suffering  ...  Customized hardwire based common characteristics of both the programmable technology like ASICs provides a high performance grade processors and hardwired ASICs.  ... 
doi:10.1016/s1383-7621(03)00068-7 fatcat:weqgn7zw6ndcpggtkwcfcgtj44

Efficient FPGA Implementation of OpenCL High-Performance Computing Applications via High-Level Synthesis

Fahad Bin Muslim, Liang Ma, Mehdi Roozmeh, Luciano Lavagno
2017 IEEE Access  
Both the host and kernel code in CPU emulation are run on the x86 based processor [10] .  ...  It was concluded that FPGAs (mainly due to their hardwired control structure) offer greater energy efficiency in comparison to GPUs.  ... 
doi:10.1109/access.2017.2671881 fatcat:t2l3cjqzc5hg3a2amiff4tiek4

Compiling high throughput network processors

Maysam Lavasani, Larry Dennison, Derek Chiou
2012 Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays - FPGA '12  
In addition, it is demonstrated how Gorilla can be used to generate merged virtual routers, saving FPGA resources.  ...  Gorilla achieves high performance and low power through the use of FPGA-tailored parallelization techniques and application-specific hardwired accelerators, processing engines, and communication mechanisms  ...  Gorilla separates the work of domain experts from the work of hardware experts, enabling each to work in their area of expertise and automatically and efficiently combining that work.  ... 
doi:10.1145/2145694.2145709 dblp:conf/fpga/LavasaniDC12 fatcat:xdotup5uavc6hh5sqkkarttj6a

Basics of Reconfigurable Computing [chapter]

Reiner Hartenstein, Tu Kaiserslautern
2007 Designing Embedded Processors  
With the von Neumann's classical software processor only the algorithm is variable, whereas the resources are fixed (hardwired), so that only one type of source code is needed: software (fig 17 b) , from  ...  Its configware code (reconfiguration code [89]: fig 10) is stored in a distributed RAM memory.  ... 
doi:10.1007/978-1-4020-5869-1_20 fatcat:2uyk5ixupfdorl4ou7apk2q4ra
« Previous Showing results 1 — 15 out of 118 results