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Efficient Hashing with Lookups in two Memory Accesses [article]

Rina Panigrahy
2004 arXiv   pre-print
In fact, with n buckets, even if the space for two items are pre-allocated per bucket, as may be desirable in hardware implementations, more than n items can be stored giving a high memory utilization.  ...  This leads to the concept of two-way hashing where the largest bucket contains O( n) balls with high probability. The hash look up will now search in both the buckets an item hashes to.  ...  I also wish to thank Artur Czumaj for providing me with a draft of his paper [7] .  ... 
arXiv:cs/0407023v1 fatcat:f2qvyiexkrc4bp4ndgokazvmmq

A hardware acceleration scheme for memory-efficient flow processing

Xin Yang, Sakir Sezer, Shane O'Neill
2014 2014 27th IEEE International System-on-Chip Conference (SOCC)  
With two lookup paths presented in the hash table together with advanced memory access scheduling techniques, DDR SDRAM access latency can be compensated.  ...  With an optimized load balancer, high bus efficiency can be achieved in the Flow LUT by swapping banks and grouping memory read/write access requests in order to issue long bursts of reads or writes to  ... 
doi:10.1109/socc.2014.6948969 dblp:conf/socc/YangSO14 fatcat:mwz4cq5conaihfm3lm7oa2ht3u

DDR3 based lookup circuit for high-performance network processing

Xin Yang, Sakir Sezer, John McCanny, Dwayne Burns
2009 2009 IEEE International SOC Conference (SOCC)  
As such, efficient DDR bandwidth utilization is a major challenge for lookup functions that exhibit short and random memory access patterns.  ...  Figure 2 Figure 1 : 21 Hash-CAM lookup circuit using D Figure 3 : 3 Data Figure 4 : 4 For each hash value (CRC_addr), the DDR3 controller returns two output values in two clock Command State Diagrams  ... 
doi:10.1109/soccon.2009.5398024 dblp:conf/socc/YangSMB09 fatcat:f4otafsplvdkbapk4z5muqrosq

MemC3: Compact and Concurrent MemCache with Dumber Caching and Smarter Hashing

Bin Fan, David G. Andersen, Michael Kaminsky
2013 Symposium on Networked Systems Design and Implementation  
We have implemented these modifications in a system we call MemC3-Memcached with CLOCK and Concurrent Cuckoo hashing-but believe that they also apply more generally to many of today's read-intensive, highly  ...  This paper presents a set of architecturally and workloadinspired algorithmic and engineering improvements to the popular Memcached system that substantially improve both its memory efficiency and throughput  ...  Compared with Memcached's original chaining-based hash table, our design improves memory efficiency by applying cuckoo hashing [23] -a practical, advanced hashing scheme with high memory efficiency and  ... 
dblp:conf/nsdi/FanAK13 fatcat:uujb4vp6djhadnrdnrg2acplbm

Longest prefix matching using bloom filters

S. Dharmapurikar, P. Krishnamurthy, D.E. Taylor
2006 IEEE/ACM Transactions on Networking  
Using less than 2Mb of embedded RAM and a commodity SRAM device, our technique achieves average performance of one hash probe per lookup and a worst case of two hash probes and one array access per lookup  ...  prefix lengths in the forwarding table given that memory resources scale linearly with the number of prefixes in the forwarding table.  ...  We later show how the worst case can be limited to two hash probes and one array access per lookup by trading off some memory efficiency.  ... 
doi:10.1109/tnet.2006.872576 fatcat:5pvcofat5fhe7ntbetofg7srem

Longest prefix matching using bloom filters

Sarang Dharmapurikar, Praveen Krishnamurthy, David E. Taylor
2003 Proceedings of the 2003 conference on Applications, technologies, architectures, and protocols for computer communications - SIGCOMM '03  
Using less than 2Mb of embedded RAM and a commodity SRAM device, our technique achieves average performance of one hash probe per lookup and a worst case of two hash probes and one array access per lookup  ...  prefix lengths in the forwarding table given that memory resources scale linearly with the number of prefixes in the forwarding table.  ...  We later show how the worst case can be limited to two hash probes and one array access per lookup by trading off some memory efficiency.  ... 
doi:10.1145/863977.863979 fatcat:aejhogwrtvefde56f4gfplfsni

Longest prefix matching using bloom filters

Sarang Dharmapurikar, Praveen Krishnamurthy, David E. Taylor
2003 Proceedings of the 2003 conference on Applications, technologies, architectures, and protocols for computer communications - SIGCOMM '03  
Using less than 2Mb of embedded RAM and a commodity SRAM device, our technique achieves average performance of one hash probe per lookup and a worst case of two hash probes and one array access per lookup  ...  prefix lengths in the forwarding table given that memory resources scale linearly with the number of prefixes in the forwarding table.  ...  We later show how the worst case can be limited to two hash probes and one array access per lookup by trading off some memory efficiency.  ... 
doi:10.1145/863955.863979 dblp:conf/sigcomm/DharmapurikarKT03 fatcat:7kateructzbhzdrmd7q2avjxpe

NameFilter: Achieving fast name lookup with low memory cost via applying two-stage Bloom filters

Yi Wang, Tian Pan, Zhian Mi, Huichen Dai, Xiaoyu Guo, Ting Zhang, Bin Liu, Qunfeng Dong
2013 2013 Proceedings IEEE INFOCOM  
Moreover, we optimize the hash value calculation of name strings, as well as the data structure to store multiple Bloom filters, which significantly reduces the memory access times compared with that of  ...  In this paper we design, implement and evaluate NameFilter, a two-stage Bloom filter-based scheme for Named Data Networking name lookup, in which the first stage determines the length of a name prefix,  ...  To conquer the above challenges, we investigate constructing efficient name lookup engines using Bloom filter [3] , which has the following two advantages: 1) High memory efficiency.  ... 
doi:10.1109/infcom.2013.6566742 dblp:conf/infocom/WangPMDGZLD13 fatcat:ohbvstpsbzaudcjqrptumzoknu

A hash-based scalable IP lookup using Bloom and fingerprint filters

Heeyeol Yu, Rabi Mahapatra, Laxmi Bhuyan
2009 2009 17th IEEE International Conference on Network Protocols  
The simulation with large scale routing tables shows that our IP lookup scheme offers 4.5 and 50.1 times memory and power efficiencies than other contemporary hash and TCAM schemes, respectively. 978-1  ...  Hashbased architectures have lookup schemes that are recognized for being both power and memory efficient due to their O(1) lookup, in contrast to other contemporary architectures.  ...  Our IP Lookup Architecture with a PIHT Hash-based IP lookup schemes have received favorable attention because of power and memory efficiency [11, 12] .  ... 
doi:10.1109/icnp.2009.5339676 dblp:conf/icnp/YuMB09 fatcat:izkhk4sr3reetnnq36ab3hln4m

Scalable, high performance ethernet forwarding with CuckooSwitch

Dong Zhou, Bin Fan, Hyeontaek Lim, Michael Kaminsky, David G. Andersen
2013 Proceedings of the ninth ACM conference on Emerging networking experiments and technologies - CoNEXT '13  
This paper presents CUCKOOSWITCH, a software-based Ethernet switch design built around a memory-efficient, high-performance, and highly-concurrent hash table for compact and fast FIB lookup.  ...  We show that CUCKOOSWITCH can process 92.22 million minimumsized packets per second on a commodity server equipped with eight 10 Gbps Ethernet interfaces while maintaining a forwarding table of one billion  ...  With batching, using our two-round prefetching strategy to reduce the overall memory bandwidth use, we can process n packets, when n is appropriately large, in two memory-access latencies with only 1.5  ... 
doi:10.1145/2535372.2535379 dblp:conf/conext/ZhouFLKA13 fatcat:kg76xcjpvbh3rjj4o4za622mqq

High speed IP address lookup architecture using hashing

Hyesook Lim, Ji-Hyun Seo, Yeo-Jin Jung
2003 IEEE Communications Letters  
two memory accesses in average.  ...  Hashing functions are applied to each address lookup table in order to find out matching entries in parallel, and the entry matched with the longest prefix among them is selected.  ...  two memory accesses in average.  ... 
doi:10.1109/lcomm.2003.818885 fatcat:2u4imlj5ajednmmwwtjb73akle

Cuckoo Trie: Exploiting Memory-Level Parallelism for Efficient DRAM Indexing [article]

Adar Zeitak, Adam Morrison
2022 arXiv   pre-print
The Cuckoo Trie is designed to have memory-level parallelism -- which a modern out-of-order processor can exploit to execute DRAM accesses in parallel -- without sacrificing memory efficiency.  ...  We present the Cuckoo Trie, a fast, memory-efficient ordered index structure.  ...  Acknowledgments This work was funded in part by ISF under grant 2005/17, Blavatnik ICRC at TAU, and the Blavatnik Family Foundation.  ... 
arXiv:2201.09331v1 fatcat:ig367khr3vbrvp3jmsvh3foxau

A Novel Scalable and Storage-Efficient Architecture for High Speed Exact String Matching

Ali Peiravi, Mohammad Javad Rahimzadeh
2009 ETRI Journal  
To keep pace with high network speeds, specialized hardware-based solutions are needed which should be efficient enough to maintain scalability in terms of speed and the number of strings.  ...  The proposed scheme is implemented in reconfigurable hardware and we compare it with existing solutions.  ...  The architecture has 2 hash functions, and in order to perform 2 concurrent memory accesses, a dual-port memory with the required lookup table size is used as described in section V.2.  ... 
doi:10.4218/etrij.09.0108.0353 fatcat:4softtr3sncirepwi67v44mequ

A new IP lookup cache for high performance IP routers

Guangdeng Liao, Heeyeol Yu, Laxmi Bhuyan
2010 Proceedings of the 47th Design Automation Conference on - DAC '10  
IP lookup is in the critical data path in a high speed router. In this paper, we propose a new on-chip IP cache architecture for a high performance IP lookup.  ...  We design the IP cache along two important axes: cache indexing and cache replacement policies. First, we study various hash performance and employ 2-Universal hashing for our IP cache.  ...  Before offchip hash table accesses, the expensive off-chip access requests are filtered out by using Bloom filters so a memory-efficient approximate membership query is warranted.  ... 
doi:10.1145/1837274.1837361 dblp:conf/dac/LiaoYB10 fatcat:heuhhumjavgtrjqmt2ifhvcp2m

Guided multiple hashing: Achieving near perfect balance for fast routing lookup

Xi Tao, Yan Qiao, Jih-Kwon Peir, Shigang Chen, Zhuo Huang, Shih-Lien Lu
2013 2013 21st IEEE International Conference on Network Protocols (ICNP)  
Hash-based lookup has been a research focus in this area due to its O(1) average lookup time, as compared to other approachs such as trie-based lookup which tends to make more memory accesses.  ...  Our simulation results show that with the same number of hash functions, the guided multiplehashing schemes are more balanced than d-left and others, while the average number of buckets to be accessed  ...  We also show the lookup efficiency change in Figure 10 with m = 150K.  ... 
doi:10.1109/icnp.2013.6733607 dblp:conf/icnp/TaoQPCHL13 fatcat:deevj4bmj5frphq3jjxqx2u32u
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