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An FPGA-based architecture for real time image feature extraction

D.G. Bariamis, D.K. Iakovidis, D.E. Maroulis, S.A. Karkanis
2004 Proceedings of the 17th International Conference on Pattern Recognition, 2004. ICPR 2004.  
These features are angular second moment, correlation, inverse difference moment, and entropy. The proposed architecture consists of a hardware and a software module.  ...  The software retrieves the feature vectors calculated in hardware and performs complementary computations. The architecture was evaluated using standard grayscale images and video clips.  ...  Acknowledgments This work was realized under the framework of the Operational Program for Education and Vocational Training Project Pythagoras cofunded by European Union and the Ministry of National Education  ... 
doi:10.1109/icpr.2004.1334338 dblp:conf/icpr/BariamisIMK04 fatcat:zlexpfc455cy7dz5hkgqeme7ae

The LRPD test

Lawrence Rauchwerger, David Padua
1995 SIGPLAN notices  
We illustrate several ways to exploit those features from a code which computes Zernike moments, using two different formulations: direct and iterative.  ...  This work analyzes the most advanced features of the Kepler GPU by Nvidia, mainly dynamic parallelism for launching kernels internally from the GPU and thread scheduling via Hyper-Q.  ...  We also thank NVIDIA for hardware donation under CUDA Teaching Center 2011-14, CUDA Research Center 2012-14 and CUDA Fellow 2012-14 Awards.  ... 
doi:10.1145/223428.207148 fatcat:afcjmnqe5zeh5cu45lhow5wlwe

Parallel Reconfigurable Hardware Implementations For The Lifting-Based Discrete Wavelet Transform

Mohamed Jemni, Sami Khanfir
2008 Zenodo  
Publication in the conference proceedings of EUSIPCO, Lausanne, Switzerland, 2008  ...  HARDWARE ARCHITECTURE FOR DWT LIFTING-BASED ALGORITHM The goal of this work is to propose a high memory throughput architecture to treat large size images as well as real-time DWT processing for video  ...  Finally the use of these two architectures could be extremely helpful for real-time image processing systems of large size images.  ... 
doi:10.5281/zenodo.40821 fatcat:oblehill75ed7goa3rkfg447om

Special issue (part II) on parallel computing for real-time image processing

Mohamed Akil, Laurent Perroton
2011 Journal of Real-Time Image Processing  
image and video processing as related to parallel computing or real-time implementation of embedded image processing applications on parallel architectures including multi-core platforms, graphics processors  ...  We have organized this special issue on Parallel Computing for Real-Time Image Processing to present the current state-of-the-art in the field of parallel programming and the future trends in realtime  ...  His research interests are architecture for image processing, image compression, reconfigurable architecture and FPGA, high-level design methodology for multi-FPGA, mixed architecture (DSP/FPGA), system  ... 
doi:10.1007/s11554-011-0210-0 fatcat:hwmsn52suzakdhvfemgo3asnim

High Performance Vlsi Architecture Of 2D Discrete Wavelet Transform With Scalable Lattice Structure

Juyoung Kim, Taegeun Park
2009 Zenodo  
Furthermore, the proposed 2D DWT processes in horizontal and vertical directions simultaneously without an idle period, so that it computes the DWT for an N×N image in a period of N2(1-2-2J)/3.  ...  The proposed architecture requires about 2MN-3N registers to save the intermediate results for higher level decomposition, where M and N stand for the filter length and the row width of the image respectively  ...  for the filter length and the row width of the image respectively.  ... 
doi:10.5281/zenodo.1334205 fatcat:44jb2q2hu5esdavqo5ylbtttoi

Hardware Architecture for Pattern Recognition in Gamma-Ray Experiment

Sonia Khatchadourian, Jean-Christophe Prévotet, Lounis Kessal
2009 EURASIP Journal on Embedded Systems  
This trigger is based on a neural system that extracts the interesting features of the incoming images and rejects the background more efficiently than classical solutions.  ...  In this article, we present the basic principles of the algorithms as well as their hardware implementation in FPGAs (Field Programmable Gate Arrays).  ...  Hardware Implementation of Zernike Moments. Although very efficient, Zernike moments are known for their computation complexity.  ... 
doi:10.1155/2009/737689 fatcat:z6zkcg6jyvgjtipdau7lpej3fy

FPGA-based ORB Feature Extraction for Real-Time Visual SLAM [article]

Weikang Fang, Yanjun Zhang, Bo Yu, Shaoshan Liu
2017 arXiv   pre-print
Simultaneous Localization And Mapping (SLAM) is the problem of constructing or updating a map of an unknown environment while simultaneously keeping track of an agent's location within it.  ...  Hence, in this paper, we design, implement, and evaluate a hardware ORB feature extractor and prove that our design is a great balance between performance and energy consumption compared with ARM Krait  ...  The latency of the hardware for processing an image is 14.8ms, and the througput of the hardware is 67 frames per second.  ... 
arXiv:1710.07312v1 fatcat:srtbih4jdfhwzejgw23ga7qsfm

Dedicated Hardware for Real-Time Computation of Second-Order Statistical Features for High Resolution Images [chapter]

Dimitris Bariamis, Dimitris K. Iakovidis, Dimitris Maroulis
2006 Lecture Notes in Computer Science  
We present a novel dedicated hardware system for the extraction of second-order statistical features from high-resolution images.  ...  The experimental results illustrate the feasibility of real-time feature extraction for input images of dimensions up to 2048×2048 pixels, where a performance of 32 images per second is achieved.  ...  Acknowledgement This research was funded by the Operational Program for Education and Vocational Training (EPEAEK II) under the framework of the project "Pythagoras -Support of  ... 
doi:10.1007/11864349_7 fatcat:5vlcyeigzjgtrnp27lhaehbszm

Page 54 of Journal of Research and Practice in Information Technology Vol. 9, Issue 2 [page]

1977 Journal of Research and Practice in Information Technology  
i. is the length of segment i. : iieh Figure 1: A segment table for a process-image consisting of n segments 54 The Australian Computer Journal, Vol. 9, No. 2, July 1977  ...  of programs may exist (e.g. in a time sharing system). c) Efficient use of main store for variable length tables, etc.  ... 

An Efficient Hardware Architecture for Multimedia Encryption and Authentication Using the Discrete Wavelet Transform

Amit Pande, Joseph Zambreno
2009 2009 IEEE Computer Society Annual Symposium on VLSI  
It allows building a keyspace for lightweight multimedia encryption. The parameterization yields rational coefficients leading to an efficient fixed point hardware implementation.  ...  Comparison with existing approaches was performed to indicate the high throughput and low hardware overhead in adding the security feature to the DWT architecture.  ...  The increasing importance of the DWT in image and multimedia compression applications has inspired the development of efficient hardware for implementations.  ... 
doi:10.1109/isvlsi.2009.26 dblp:conf/isvlsi/PandeZ09 fatcat:retaow3dqveqjjxda2kp67q2he

Fpga Based Parallel Architecture For The Computation Of Third-Order Cross Moments

Syed Manzoor Qasim, Shuja Abbasi, Saleh Alshebeili, Bandar Almashary, Ateeq Ahmad Khan
2008 Zenodo  
Algorithms used for the computation of cross moments are computationally intensive and require high computational speed for real-time applications.  ...  In this paper, we present FPGA-based parallel architecture for the computation of third-order cross moments.  ...  [5] presented a computationally efficient VLSI architecture for the computation of third-order cumulants.  ... 
doi:10.5281/zenodo.1333891 fatcat:zmztelsy6rhxvnp7tt3avvddpy

Pipeline architectures of Three-dimensional daubechies wavelet transform using hybrid method

Noor Huda Ja'afar, Afandi Ahmad
2019 Indonesian Journal of Electrical Engineering and Computer Science  
The proposed pipelined architectures are deployed for adaptive transformation process of medical image compression applications.  ...  <span>The application of three-dimensional (3-D) medical image compression systems uses several building blocks for its computationally intensive algorithms to perform matrix transformation operations.  ...  CONCLUSION Two architectures for 3-D Daub4 and Daub6 have been proposed in this paper based on transpose computation for transform block of medical image compression.  ... 
doi:10.11591/ijeecs.v15.i1.pp240-246 fatcat:xu45y3s5yvfzfhw7csj5qkcr4m

Page 50 of Astronomy and Astrophysics Vol. 144, Issue 1 [page]

1985 Astronomy and Astrophysics  
DEC VT125 terminals for low-level graphics and a Sigma ARGS 7000 video processor for image display.  ...  Therefore an efficient structure for the management of disk memory has been adopted (Pasian et al., 1983). This structure provides memory mapping of data stored on disk, so that the user  ... 

FPGA-based real-time object tracking for mobile robot

Xiaofeng Lu, Diqi Ren, Songyu Yu
2010 2010 International Conference on Audio, Language and Image Processing  
This paper proposes an embedded vision system for real-time moving object tracking using modified meanshift algorithm for mobile robot application.  ...  This hardware implementation realizes time-consumed color space transformation using pipeline operations, which completely removes the dependence of off-chip RAM memory.  ...  Acknowledgement This research was supported in part by NSFC (60702044), Innovation foundation of Shanghai University (A10-0107-09-902).  ... 
doi:10.1109/icalip.2010.5685091 fatcat:coi55gcn2rf77no4pvpt47zzqq

Journal of Real-Time Image Processing: second issue of volume 14

Nasser Kehtarnavaz, Matthias F. Carlsohn
2018 Journal of Real-Time Image Processing  
A hardware architecture is proposed that exploits the computing power of FPGAs by clustering pixels in parallel.  ...  This paper discusses the design of a partial overlapping block using exact Legendre moment computation (named POBRELM) for gray-level image reconstruction.  ... 
doi:10.1007/s11554-018-0761-4 fatcat:nc6szx5lafatxa7lfiif64nafa
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