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Massively Parallel Logic Simulation with GPUs
2011
ACM Transactions on Design Automation of Electronic Systems
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In this article, we developed a massively parallel gate-level logical simulator to address the ever-increasing computing demand for VLSI verification. ...
This work proves that the CMB algorithm can be efficiently and effectively deployed on modern GPUs without the performance overhead that had hindered its successful applications on previous parallel architectures ...
The event-driven logic simulation is a very efficient sequential algorithm. ...
doi:10.1145/1970353.1970362
fatcat:cvmbvmbpy5f7bbcahpc5ir6x5q
Parallelizing a discrete event simulation application using the Habanero-Java multicore library
2015
Proceedings of the Sixth International Workshop on Programming Models and Applications for Multicores and Manycores - PMAM '15
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Discrete event simulation (DES) has been widely adopted for simulating communication systems such as computer networks. ...
While the DES problem benefits greatly from HJlib's support for lightweight tasks and efficient parallelism based on work stealing, it also pushed the boundaries of the standard primitives available in ...
Performance evaluation results for both Galois and our HJlib versions of parallel logic circuit simulation are shown in Section 5. ...
doi:10.1145/2712386.2712402
dblp:conf/ppopp/XiaoZS15
fatcat:p32jz34sqvf7xejytqvrz2ddty
Distributed time, conservative parallel logic simulation on GPUs
2010
Proceedings of the 47th Design Automation Conference on - DAC '10
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With carefully designed data structures and data flow organizations, our GPU based simulator could overcome many problems that hindered efficient implementations of the CMB algorithm on traditional parallel ...
To expose more parallelism, we implemented a conservative parallel simulation approach, the CMB algorithm, on NVidia GPUs. ...
ACKNOWLEDGEMENT This work was partially supported by Tsinghua CUDA Center of Excellence and an Intel University program. The authors also appreciate hardware donation from NVidia. ...
doi:10.1145/1837274.1837467
dblp:conf/dac/WangZD10
fatcat:r3zzogypnbctxjxbz3jwc5bqgy
Parallel logic simulation of VLSI systems
1995
Proceedings of the 32nd ACM/IEEE conference on Design automation conference - DAC '95
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This tutorial describes the current state-of-the-art in parallel logic simulation, including parallel simulation techniques, factors that impact simulation performance, performance results to date, and ...
As a result, researchers are attempting to exploit parallel processing techniques to improve the performance of VLSI logic simulation. ...
ACKNOWLEDGMENT The author would like to thank Mary Bailey for her insightful comments on an early draft of this manuscript. ...
doi:10.1145/217474.217520
dblp:conf/dac/Chamberlain95
fatcat:r7pbllgnnzaytedlvbd6blno4m
Parallel Logic Simulation of VLSI Systems
1995
Proceedings - Design Automation Conference
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This tutorial describes the current state-of-the-art in parallel logic simulation, including parallel simulation techniques, factors that impact simulation performance, performance results to date, and ...
As a result, researchers are attempting to exploit parallel processing techniques to improve the performance of VLSI logic simulation. ...
ACKNOWLEDGMENT The author would like to thank Mary Bailey for her insightful comments on an early draft of this manuscript. ...
doi:10.1109/dac.1995.250078
fatcat:6z2noirad5gllocr7vab4yokqu
Evaluation of parallel logic simulation using DVSIM
1996
Proceedings of HICSS-29: 29th Hawaii International Conference on System Sciences
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Parallel simulation is expected to speed up simulation run time in a significant way. This paper describes a framework that is used to evaluate the performance of parallel simulation algorithms. ...
The framework's core is DVSIM, a parallel event-driven VHDL simulator. The framework provides several mechanisms to calculate sensible bases for speed-up calculation. ...
Furthermore, it is assumed that each event is executed as early as possible (i.e., an event is evaluated if it is known and if all events for the corresponding gate with smaller time stamps have been executed ...
doi:10.1109/hicss.1996.495487
dblp:conf/hicss/Meister96
fatcat:4r4jnx3jz5c5vigmw6ehuux3si
High performance gate-level simulation with GP-GPU computing
2011
Proceedings of 2011 International Symposium on VLSI Design, Automation and Test
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It is no surprise that the EDA and semiconductor industries are always seeking for faster simulation solutions. ...
Based on these observations, we propose novel algorithms for the efficient mapping of large netlists to the concurrent architecture of GPU hardware. ...
parallelism by leveraging alternative algorithms suitable for efficient execution on a GPU platform. ...
doi:10.1109/vdat.2011.5783577
fatcat:myt3bsnwqnfhjim4q4po3idxui
An evaluation of the Chandy-Misra-Bryant algorithm for digital logic simulation
1991
ACM Transactions on Modeling and Computer Simulation
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logic simulation. ...
We explore the suitablhty of the Chandy-Misra-Bry ant (CMB) algorithm for the domain of di@al lo~c simulation. ...
to the event-driven
algorithm
for parallel
digital
logic simulation. ...
doi:10.1145/130611.130613
fatcat:3lki7xqyejgpxmug6q6bxo7yna
Parallel Discrete Event Simulation as a Paradigm for Large Scale Modeling Experiments
2015
International Conference on Data Analytics and Management in Data Intensive Domains
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Parallel Discrete Event Simulation (PDES) is a method introduced to conduct simulation of a complex system, which consists of a large number of objects. ...
The PDES has been known for about 30 years and we discuss why further analysis of the method is important nowadays. ...
Second, it is assumed that it is possible to handle several LPs within one PE, and that communication within PE may be efficient using conservative algorithm. ...
dblp:conf/rcdl/ShchurS15
fatcat:y3y2ifmpifei7hrejifcqo23cm
Experimental analysis of logical process simulation algorithms in JAMES II
2009
Proceedings of the 2009 Winter Simulation Conference (WSC)
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The notion of logical processes is a widely used modeling paradigm in parallel and distributed discrete-event simulation. ...
of simulation algorithms for logical processes. ...
By supporting the logical process metaphor, we broaden the scope of JAMES II and address the particularly challenging field of evaluating parallel and distributed discrete-event simulation algorithms. ...
doi:10.1109/wsc.2009.5429633
dblp:conf/wsc/WangHEYU09
fatcat:3mnhg2rofzcbniin5is42ggr6q
Parallel logic simulation of VLSI systems
1994
ACM Computing Surveys
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Fast, efficient logic simulators are an essential tool in modern VLSI system design. ...
ACM Computing
Surveys, Vol 26, No, 3, September
1994
of parallel
computations.
Cornmun,
ACM
24,
1990.
Efficient
par-
allel logic simulation
techniques
for the Con-
nection Machine. ...
Obviously, obtaining good performance from parallel logic simulation is nontrivial. ...
doi:10.1145/185403.185424
fatcat:zvoo2ptninbmvlcehkod5wthfq
Cunetsim: A New Simulation Framework for Large Scale Mobile Networks
2012
Proceedings of the Fifth International Conference on Simulation Tools and Techniques
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To enable efficient packet-level simulation for large scale scenario, we introduce a CPU-GPU co-simulation framework where synchronization and experiment design are performed in CPU and node's logical ...
Simulation results show that Cunetsim execution time remains stable and that it achieves significantly lower execution time than existing approach when computing mobility and connectivity with no degradation ...
It provides a CPU-GPU co-simulation framework for testing and validating network protocols and algorithms for large scale scenarios. ...
doi:10.4108/icst.simutools.2012.247763
dblp:conf/simutools/RomdhanneN12
fatcat:gau5p4p2ujdbzng64y3pzje364
A tool for simulating parallel branch-and-bound methods
2016
Open Engineering
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This paper presents a tool for simulating parallel Branchand-Bound method. ...
The major difficulty in parallel B&B method is the need for dynamic load redistribution. Therefore design and study of load balancing algorithms is a separate and very important research topic. ...
The simulator The simulator was designed for convenient fast and efficient performance testing of parallel schedulers. ...
doi:10.1515/eng-2016-0031
fatcat:vlrdrzsha5d57oez6svernz5xy
Parallel and Distributed Simulation: Methodologies and Techniques
1998
Journal of King Saud University: Computer and Information Sciences
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An introduction to the field of Parallel and Distributed Simulation (PADS) is given. The capabilities and limitations of currently used PADS techniques are discussed. ...
A review of the recently developed hybrid and adaptive PADS techniques is also given. Sample perfonnance results of some PADS techniques are presented using a network of workstations. ...
Nandy and Loucks [38] presented a static partitioning algorithm for conservative parallel logic simulation. ...
doi:10.1016/s1319-1578(98)80003-7
fatcat:dmhp2qkg5vhqhjwbs6ycjvtycq
Data parallel fault simulation
1999
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
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In this paper, we discuss a novel technique to partition the fault set for data parallel fault simulation. When applied statically, the technique can scale well for up to eight processors. ...
The fault set partitioning technique is simple, can itself be parallelized, and can be implemented with extreme ease. ...
Hereon, we will refer to this as the event workload. The event workload is a measure which accounts for the number of gate evaluations as well as the cost of each evaluation. ...
doi:10.1109/92.766745
fatcat:zpabnkbthfdjrialwejlubcvb4
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