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Efficient characterization of TSV-to-transistor noise coupling in 3D ICs

Hailang Wang, Mohammad H. Asgari, Emre Salman
2013 Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI - GLSVLSI '13  
A methodology is proposed to characterize TSV induced noise coupling in three-dimensional (3D) integrated circuits.  ...  A compact π model is proposed to efficiently estimate the coupling noise at a victim transistor.  ...  CONCLUSIONS TSV-to-transistor noise coupling has been evaluated and quantified in 3D ICs.  ... 
doi:10.1145/2483028.2483064 dblp:conf/glvlsi/WangAS13 fatcat:evkvjzk3mvgzdn367ltfdirmam

Compact model to efficiently characterize TSV-to-transistor noise coupling in 3D ICs

Hailang Wang, Mohammad H. Asgari, Emre Salman
2014 Integration  
A methodology is proposed to characterize through silicon via (TSV) induced noise coupling in threedimensional (3D) integrated circuits.  ...  A compact π model is proposed to efficiently estimate the coupling noise at a victim transistor.  ...  Conclusions TSV-to-transistor noise coupling has been evaluated and quantified in 3D ICs.  ... 
doi:10.1016/j.vlsi.2013.10.006 fatcat:4rlgt7nknndkjmvsjreuuamxpm

Experience with 3D integration technologies in the framework of the ATLAS pixel detector upgrade for the HL-LHC

D. Aruntinov, M. Barbero, L. Gonella, T. Hemperek, F. Hügging, H. Krüger, N. Wermes, P. Breugnon, B. Chantepie, J.C. Clemens, R. Fei, D. Fougeron (+5 others)
2013 Nuclear Instruments and Methods in Physics Research Section A : Accelerators, Spectrometers, Detectors and Associated Equipment  
R&D focuses on both, IC design in 3D, as well as on post-processing 3D technologies such as Through Silicon Via (TSV).  ...  As discussed in the paper, this technology can still present technical challenges for the industrial partners. The second one consists of etching the TSV via last.  ...  One possibility to meet these requirements is offered by 3D integration technologies. In particular, 3D IC design and post-processing TSV are investigated.  ... 
doi:10.1016/j.nima.2013.04.044 fatcat:xjqw4dywcbb4vooksgqfuwwsei

Robust signaling techniques for through silicon via bundles

Krishna C. Chillara, Jinwook Jang, Wayne P. Burleson
2011 Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI - GLSVLSI '11  
3D ICs Signaling over TSVs Most of the earlier work has been focused on electrical modeling and characterization of TSVs and very little has been explored on signaling techniques for 3D ICs.  ...  The supply noise amplitude in stacked 3D ICs is found to be as high as 10% of the supply voltage for a stack of 2 dies.  ... 
doi:10.1145/1973009.1973089 dblp:conf/glvlsi/ChillaraJB11 fatcat:i6fikoskfbcqhcj7a2ch6fplii

On-Chip Testing Schemes of Through-Silicon-Vias (TSVs) in 3D Stacked ICs

Shadi MS. Harb, William R. Eisenstadt
2017 Advances in Science, Technology and Engineering Systems  
This paper presents on-chip testing structures to characterize and detect faulty Through Silicon Vias (TSVs) in 3D ICs technology. 3D Gunning Transceiver Logic (GTL) I/O testing is proposed to characterize  ...  the performance of 3D TSVs in high speed applications.  ...  GTL Circuit Architecture in 3D Stacked ICs A Gunning Transceiver Logic (GTL) I/O test circuit can be utilized to characterize the performance of the 3D TSVs under high speed transient simulation in 3D  ... 
doi:10.25046/aj0203159 fatcat:oz57blbpqbf7bi2mqc5xmpgady

Capacitive Coupling Mitigation for TSV-based 3D ICs

Ashkan Eghbal, Pooria M. Yaghini, Nader Bagherzadeh
2015 2015 IEEE 33rd VLSI Test Symposium (VTS)  
The latency effect of TSV-to-TSV capacitive coupling for different characteristics of a TSV using circuit-level model is presented in this article.  ...  TSV-to-TSV capacitive coupling has large disruptive effects on timing requirements of the circuit.  ...  TSVs are known as noticeable sources of coupling noise that deteriorate the Signal Integrity (SI) of 3D IC layouts in literature [3] .  ... 
doi:10.1109/vts.2015.7116279 dblp:conf/vts/EghbalYB15 fatcat:qzzrpuqj45bm3g2mnxdz4msqki

Physical Design Automation for 3D Chip Stacks

Johann Knechtel, Jens Lienig
2016 Proceedings of the 2016 on International Symposium on Physical Design - ISPD '16  
However, a multitude of challenges has thus far obstructed large-scale transition from "classical" 2D chips to stacked 3D chips.  ...  The concept of 3D chip stacks has been advocated by both industry and academia for many years, and hailed as one of the most promising approaches to meet ever-increasing demands for performance, functionality  ...  Arrangement of TSVs: For power/ground (PG) TSVs, a distributed, irregular topology is superior to both regularly placed (single) TSVs and clustered TSVs in order to limit power noise [22, 23] .  ... 
doi:10.1145/2872334.2872335 dblp:conf/ispd/KnechtelL16 fatcat:3kigpmhpnjahbow2yptm2cjrzm

On the parametric failures of SRAM in a 3D-die stack considering tier-to-tier supply cross-talk

Wen Yueh, Subho Chatterjee, Amit Trivedi, Saibal Mukhopadhyay
2012 2012 IEEE 30th VLSI Test Symposium (VTS)  
The analysis shows that due to the supply cross-talk power variation in cores modulates the performances and parametric failures in SRAM.  ...  This paper analyzes the supply crosstalk between logic cores and SRAMs on separate tiers in a 3D die-stack using a distributed RLC based 3D power grid model.  ...  ACKNOWLEDGMENT This work is supported in part by Semiconductor Research Corp (#1836.075), National Science Foundation (CNS-1054429 and CCF-0917000), Intel Corp, and IBM Faculty Award.  ... 
doi:10.1109/vts.2012.6231064 dblp:conf/vts/YuehCTM12 fatcat:kmm4lkwuqjh2dluirzs4vcre64

Monolithic 3D-based SRAM/MRAM Hybrid Memory for an Energy-efficient Unified L2 TLB-Cache Architecture

Young-Ho Gong
2021 IEEE Access  
INDEX TERMS Monolithic 3D, cache memory, translation look-aside buffer, SRAM, MRAM, energy efficiency.  ...  According to our analysis using PARSEC benchmark applications, our proposed architecture reduces the energy consumption of L2 TLB + L2 cache by up to 97.7% (53.6% on average), compared to the baseline  ...  Furthermore, TSV-3D causes significant leakage power in TSVs and its buffer chains, which affects noise margin.  ... 
doi:10.1109/access.2021.3054021 fatcat:pdiksvmgwvewtparrr3se2xyuu

Advanced NEMS-based power management for 3D Stacked Integrated Circuits

Marius Enachescu, George Voicu, Sorin Dan Cotofana
2010 2010 International Conference on Energy Aware Computing  
we make use of the 3D potential by placing the sleep transistor (the entire power management infrastructure) on a dedicated tier of the 3D stacked Integrated Circuit.  ...  Due to the extreme low leakage current of the SG-FET our proposal results in 2 orders of magnitude static power reduction, when compared with equivalent counterparts based on traditional CMOS devices.  ...  POWER MANAGEMENT IN 3D STACKED ICS One of the emergent solutions to achieve tight chip integration is to use 3D stacking technology with Through Silicon Vias (TSVs) as interconnects between the stacked  ... 
doi:10.1109/iceac.2010.5702286 fatcat:sqxbdk45h5bplg5xnmmj7iks5m

A Performance Analysis for Interconnections of 3D ICs with Frequency-Dependent TSV Model in S-parameter

Ki Jin Han, Younghyun Lim, Youngmin Kim
2014 JSTS Journal of Semiconductor Technology and Science  
In this study, the effects of the frequencydependent characteristics of through-silicon vias (TSVs) on the performance of 3D ICs are examined by evaluating a typical interconnection structure, which is  ...  Simulation results for nine-TSV bundles having regular and staggered patterns reveal that the proposed method can characterize TSV-based 3D interconnections of any dimensions and patterns.  ...  An electrical TSV model is proposed and compared by 3D EM solver considering the semiconductor effects in [11] . Models for the coupling noise of TSV are proposed in [12] .  ... 
doi:10.5573/jsts.2014.14.5.649 fatcat:mymto43la5d2njk6uijlccy4e4

Under-FET Thermal Sensor Enabling Smart Full-Chip Run-Time Thermal Management

Cheng Li, Qi Chen, Feilong Zhang, Mengfu Di, Zijin Pan, Fei Lu, Albert Wang
2020 IEEE Journal of the Electron Devices Society  
Being able to accurately monitor self-heating of individual transistor in-operando, the under-FET temperature sensor enables smart full-chip runtime thermal management with spatial resolution down to single  ...  This paper reports design, fabrication and analysis of a novel under-transistor (under-FET) in-hole thermal sensor diode structure.  ...  co-efficient (TC) of about 1.25mV/℃ across the 0.6V to 0.9V biasing range.  ... 
doi:10.1109/jeds.2020.3022730 fatcat:f24ojn73uvg23drbzr6i6l2ke4

"Green" On-chip Inductors in Three-Dimensional Integrated Circuits

Umamaheswara Rao Tida, Varun Mittapalli, Cheng Zhuo, Yiyu Shi
2014 2014 IEEE Computer Society Annual Symposium on VLSI  
IMPACT OF 3D PROCESS PARAMETERS 4. In this section, various process parameters of 3D ICs affect the efficiency of inductive converters are studied.  ...  On the other hand, idle through-silicon-vias (TSVs) in three-dimensional integrated circuits (3D ICs) can form vertical inductors with minimal footprint and little noise coupling with horizontal traces  ... 
doi:10.1109/isvlsi.2014.117 dblp:conf/isvlsi/TidaMZS14 fatcat:4a3hgqzdvrbvpa3nze66qm5lzm

Challenges and Solutions in Emerging Memory Testing

Elena Ioana Vatajelu, Paolo Prinetto, Mottaqiallah Taouil, Said Hamdioui
2017 IEEE Transactions on Emerging Topics in Computing  
The research and prototyping of new memory technologies are getting a lot of attention in order to enable new (computer) architectures and provide new opportunities for today's and future applications.  ...  This paper overviews and discusses the challenges and the emerging solutions in testing three classes of memories: 3D stacked memories, Resistive memories and Spin-Transfer-Torque Magnetic memories.  ...  Challenges: 3D-SIC manufacturing requires additional processing steps as compared to conventional ICs; these include the forming of TSVs, thinning wafers, and stacking and bonding wafers or dies.  ... 
doi:10.1109/tetc.2017.2691263 fatcat:isbxwhpr3jatngjet2jc3r2m5e

Diagnosis of Signaling and Power Noise Using In-Place Waveform Capturing for 3D Chip Stacking

Satoshi TAKAYA, Hiroaki IKEDA, Makoto NAGATA
2014 IEICE transactions on electronics  
In addition, it is also experimentally confirmed that the signal swing can be reduced to 0.75 V for error free data transfer at 100 GByte/sec, achieving the energy efficiency of 0.21 pJ/bit. key words:  ...  The collection of in-place waveforms on vertical channels with through silicon vias (TSVs) are demonstrated among 128 vertical I/O channels distributed in 8 banks in a 9.9 mm × 9.9 mm die area.  ...  Acknowledgment This work was partly supported by NEDO in the project of the development of Functionally Innovative 3D-Integrated Circuit (Dream Chip) Technology.  ... 
doi:10.1587/transele.e97.c.557 fatcat:t4pjkt5albfolc7mdvnnfei7zu
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