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Efficient and Predictable Group Communication for Manycore NoCs [chapter]

Karthik Yagna, Onkar Patil, Frank Mueller
2016 Lecture Notes in Computer Science  
In this work, we develop efficient and predictable group communication using message passing specifically designed for large core counts in 2D mesh NoC architectures.  ...  Despite these advantages, manycores pose predictability challenges that can affect both performance and real-time capabilities.  ...  Conclusion We designed a set of efficient and predictable group communication primitives using message passing utilizing NoC architectures.  ... 
doi:10.1007/978-3-319-41321-1_20 fatcat:kz6wby24xzcfhjgpt3pty37xf4

A deadlock-free subnetting mechanism for high performance broadcasting in NoC

Xing Han, Yuzhuo Fu, Jiang Jiang, Chang Wang
2015 IEICE Electronics Express  
The present results show that subnetting supplies apparent improvement in the performance of on-chip communications mixed with both unicast and broadcast on manycore processors.  ...  We propose a flexible subnetting mechanism to build subnet for specified cores on manycore processor to address this problem. Improved hardware support also requires fewer circuits in router design.  ...  Reference [4] also shows the NoC saturates with injection rate at 5% and one-to-many traffics at 10%. Subnetting is one predictable trend for manycore processors to address this problem.  ... 
doi:10.1587/elex.12.20150688 fatcat:hx75i34innfwfpzurgtpzugcga

Characterization and modeling of multicast communication in cache-coherent manycore processors

Sergi Abadal, Raúl Martínez, Josep Solé-Pareta, Eduard Alarcón, Albert Cabellos-Aparicio
2016 Computers & electrical engineering  
Both aspects pave the way for the development and accurate evaluation of advanced NoCs in the context of manycore computing. Please cite this article as: S.  ...  His current research interests are in nanonetworking communications, traffic monitoring and analysis, high speed and optical networking, and energy efficient transport networks.  ...  This implies that applications that appear first may yield more pronounced imbalance in manycore processors and would especially benefit from NoC designs that efficiently handle hotspot situations.  ... 
doi:10.1016/j.compeleceng.2015.12.018 fatcat:wbyxjkqw45hxzbicwmwictm3yq

Improving the performance of actor model runtime environments on multicore and manycore platforms

Emilio Francesquini, Alfredo Goldman, Jean-François Méhaut
2013 Proceedings of the 2013 workshop on Programming based on actors, agents, and decentralized control - AGERE! '13  
(NUMA) and manycore processors.  ...  Based on previous work, we present our design guidelines for the RE adaptation to the Kalray MPPA-256 manycore processor.  ...  Acknowledgments The authors would like to thank CAPES for funding this research under project CAPES/Cofecub 660/10.  ... 
doi:10.1145/2541329.2541342 dblp:conf/agere/FrancesquiniGM13 fatcat:egm6wg5cl5hihmatzesjwivrya

A Manycore Vision Processor for Real-Time Smart Cameras

Bruno A. da Silva, Arthur M. Lima, Janier Arias-Garcia, Michael Huebner, Jones Yudi
2021 Sensors  
These applications bring the need for Smart Cameras for local real-time processing of images and videos.  ...  In this work, we show the design and implementation of a manycore vision processor architecture to be used in Smart Cameras.  ...  Most of the work use NoC for communication, and have programmable devices.  ... 
doi:10.3390/s21217137 pmid:34770444 pmcid:PMC8587860 fatcat:uf45ud4v6fdmdj3chrz5vcsi7y

Medium Access Control in Wireless Network-on-Chip: A Context Analysis [article]

Sergi Abadal, Albert Mestres, Josep Torrellas, Eduard Alarcón, Albert Cabellos-Aparicio
2018 arXiv   pre-print
Wireless on-chip communication is a promising candidate to address the performance and efficiency issues that arise when scaling current Network-on-Chip (NoC) techniques to manycore processors.  ...  wireline NoCs.  ...  by the Catalan Institution for Research and Advanced Studies (ICREA).  ... 
arXiv:1806.06294v1 fatcat:52zgi4h4vvafxlwyzth6sybuvq

Medium Access Control in Wireless Network-on-Chip: A Context Analysis

Sergi Abadal, Albert Mestres, Josep Torrellas, Eduard Alarcon, Albert Cabellos-Aparicio
2018 IEEE Communications Magazine  
Wireless on-chip communication is a promising candidate to address the performance and efficiency issues that arise when scaling current Network-on-Chip (NoC) techniques to manycore processors.  ...  wireline NoCs.  ...  ACKNOWLEDGMENT This work has been supported in part by NSF under grant CCF 16-29431, the European Commission under grant H2020-FETOPEN-736876 (VISORSURF), and the Spanish MINECO under contract TEC2017-  ... 
doi:10.1109/mcom.2018.1601068 fatcat:zvslslf7lbftjaq34mxst3567y

Evaluation of the Memory Communication Traffic in a Hierarchical Cache Model for Massively-Manycore Processors

Sharifa Al Khanjari, Wim Vanderbauwhede
2016 2016 24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP)  
Many researchers have focused on direct communication between cores in the NoC; however in a manycore processor the communication is actually between the cores and the memory hierarchy.  ...  A key enabler in manycore systems is the use of Networks-on-Chip (NoC) as a global communication mechanism.  ...  Performance of NoC-based manycore systems is highly dependent on the traffic patterns and the NoC topologies: in manycore systems communication, not computation, is the performance-limiting factor.  ... 
doi:10.1109/pdp.2016.30 dblp:conf/pdp/KhanjariV16 fatcat:ldyajs2epbbe7ah444zpmgkari

Energy Efficient Seismic Wave Propagation Simulation on a Low-Power Manycore Processor

Marcio Castro, Fabrice Dupros, Emilio Francesquini, Jean-Francois Mehautk, Philippe O.A. Navaux
2014 2014 IEEE 26th International Symposium on Computer Architecture and High Performance Computing  
In this paper, we analyze the use of a low-power manycore processor, the MPPA-256, for seismic wave propagation simulations.  ...  Next, we compare the performance and energy efficiency of seismic wave propagation on MPPA-256 to other commonplace platforms such as general-purpose processors and a GPU.  ...  ACKNOWLEDGEMENTS This work was supported by CAPES, the HPC-GA project funded by the FP7-PEOPLE under grant agreement number 295217 and BRGM Carnot-institute.  ... 
doi:10.1109/sbac-pad.2014.28 dblp:conf/sbac-pad/CastroDFMN14 fatcat:fhiwtovgmra45pk2t7jiv2mbem

Towards future adaptive multiprocessor systems-on-chip: An innovative approach for flexible architectures

Fabrice Lemonnier, Philippe Millet, Gabriel Marchesan Almeida, Michael Hubner, Jurgen Becker, Sebastien Pillement, Olivier Sentieys, Martijn Koedam, Shubhendu Sinha, Kees Goossens, Christian Piguet, Marc-Nicolas Morgan (+1 others)
2012 2012 International Conference on Embedded Computer Systems (SAMOS)  
This paper introduces adaptive techniques targeted for heterogeneous manycore architectures and introduces the FlexTiles platform, which consists of general purpose processors with some dedicated accelerators  ...  Dynamic adaptation will be mainly used to reduce both overall power consumption and temperature and to ease the problem of decreasing yield and reliability that results from submicron CMOS scales.  ...  For communications purpose a flexible NoC supporting different Quality of Services (QoS) will be used as communication infrastructure.  ... 
doi:10.1109/samos.2012.6404179 dblp:conf/samos/LemonnierMAHBPSKSGPML12 fatcat:vvdjjie7xzaarjn44536hcx6ny

A Flexible Software/Hardware Adaptive Network for Embedded Distributed Architectures

Celine Azar
2021 Circuits and Systems An International Journal  
We propose SNet, a new Scalable NETwork paradigm that extends the NoCs area to include a software/hardware dynamic routing mechanism.  ...  SNet has the benefit of being extremely versatile, allowing for the creation of a broad range of routing topologies to meet the needs of various applications.  ...  While NoCs are a good answer for today's network topologies, we expect that in future manycore designs with thousands of cores on chip, more efficient interconnection techniques would be provided.  ... 
doi:10.5121/csij.2021.8301 fatcat:j47qdh26anc3jjpmbsqrx66hdq

A Distributed Framework for Low-Latency OpenVX over the RDMA NoC of a Clustered Manycore

Julien Hascoe, Benoet Dupont de Dinechin, Karol Desnos, Jean-Francois Nezan
2018 2018 IEEE High Performance extreme Computing Conference (HPEC)  
OpenVX is a standard proposed by the Khronos group for cross-platform acceleration of computer vision and deep learning applications.  ...  While highly efficient OpenVX implementations exist for shared memory multi-core processors, targeting OpenVX to clustered manycore processors appears challenging.  ...  It has been designed for high energy efficiency and time predictability for critical embedded applications [4] .  ... 
doi:10.1109/hpec.2018.8547736 dblp:conf/hpec/HascoetDDN18 fatcat:ri7iejxc2ffmhk3sntlilwxniq

Analysis of computing and energy performance of multicore, NUMA, and manycore platforms for an irregular application

Márcio Castro, Emilio Francesquini, Thomas M. Nguélé, Jean-François Méhaut
2013 Proceedings of the 3rd Workshop on Irregular Applications Architectures and Algorithms - IA^3 '13  
These strict energy constraints paved the way for the development of multi and manycore processors.  ...  Research on the performance and the energy efficiency of numerical kernels on multicores are common but studies in the context of manycores are sparse.  ...  Part of this work was done in the context of the European 'Mont-Blanc: European scalable and power efficient HPC platform based on low-power embedded technology' #288777 project of call FP7-ICT-2011-7.  ... 
doi:10.1145/2535753.2535757 dblp:conf/sc/CastroFNM13 fatcat:pg7rcv5ebvejvjqik4uyotd5ru

On Topology Reconfiguration for Defect-Tolerant NoC-Based Homogeneous Manycore Systems

Lei Zhang, Yinhe Han, Qiang Xu, Xiao wei Li, Huawei Li
2009 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
Homogeneous manycore systems are emerging for tera-scale computation and typically utilize Network-on-Chip (NoC) as the communication scheme between embedded cores.  ...  We then present novel solutions for the above problem, which not only maximize the performance of the on-chip communication scheme, but also provide a unified topology to Operating System and application  ...  ACKNOWLEDGMENT The authors would like to thank the anonymous reviewers for their constructive comments.  ... 
doi:10.1109/tvlsi.2008.2002108 fatcat:hlh257nyynek3erogi5bqd2v4m

On the energy efficiency and performance of irregular application executions on multicore, NUMA and manycore platforms

Emilio Francesquini, Márcio Castro, Pedro H. Penna, Fabrice Dupros, Henrique C. Freitas, Philippe O.A. Navaux, Jean-François Méhaut
2015 Journal of Parallel and Distributed Computing  
These cores are distributed across 16 compute clusters and 4 I/O subsystems that 103 communicate through data and control NoCs.  ...  The use of Network-on-Chip (NoC) for communication and the absence 41 of cache coherence protocols are among the important factors that make the development of 42 parallel applications on this processor  ...  and I/O subsystems are connected by two parallel NoCs, the Data NoC (D-129 NoC) and the Control NoC (C-NoC).  ... 
doi:10.1016/j.jpdc.2014.11.002 fatcat:k4uf7y34yfghtkcw4bvvi7m3cu
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