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Configurable Verification Stimulus Acceleration Method Based on Multicore Processor

Pan Guoteng, Tang Yuxing, Ou Guodong, Luo Li, Yang Qingna
2014 Open Cybernetics and Systemics Journal  
To improve the efficiency of verification, it is necessary to choose appropriate verification method and tools.  ...  can shorten simulation cycle and simulation time, reduce the verification cost and guaranteed the correctness of design.  ...  ACKNOWLEDGEMENTS This work is supported by National Natural Science Foundation of China (61202123).  ... 
doi:10.2174/1874110x01408010017 fatcat:dhf5onzjbva6zazoogcqvkzd4m

A Unified Processor Model for Compiler Verification and Simulation Using ASM [chapter]

Roland Lezuo, Andreas Krall
2012 Lecture Notes in Computer Science  
Finally we present our preliminary results which indicate that a unified ASM model is sufficient for proving correct instruction selection and generating efficient cycle-accurate simulators.  ...  For safety critical embedded systems the correctness of the processor, toolchain and compiler is an important issue. Translation validation is one approach for compiler verification.  ...  To achieve efficient simulation we restrained ourselves to a static subset of the CoreASM language but nonetheless found creation of the models easy.  ... 
doi:10.1007/978-3-642-30885-7_24 fatcat:wbw7xjpflzduphgnt3c2esbw7e

Efficient formal verification of pipelined processors with instruction queues

Miroslav N. Velev
2004 Proceedins of the 14th ACM Great Lakes symposium on VLSI - GLSVLSI '04  
Without the presented method, the monolithic formal verification of 9-stage, 9-wide VLIW processors-implementing many realistic and speculative features inspired by the Intel Itanium-scaled for models  ...  Presented is a method for formal verification of pipelined processors with long instruction queues.  ...  Conclusions Presented was a method for efficient formal verification of pipelined processors with long instruction queues.  ... 
doi:10.1145/988952.988975 dblp:conf/glvlsi/Velev04 fatcat:lfgotr4qs5fo3aufubhpgzotxe

Performance Analysis of an Optimistic Simulator for CD++

Qi Liu, Gabriel Wainer
2007 40th Annual Simulation Symposium (ANSS'07)  
DEVS is a formalism to describe generic dynamic systems in a hierarchical and modular way.  ...  A two-level usercontrolled state-saving mechanism is proposed to achieve efficient and flexible state saving at runtime.  ...  As a sound formal M&S framework based on generic dynamic system concepts, the DEVS [1] formalism supports hierarchical and modular construction of models, allowing model reuse, reducing development and  ... 
doi:10.1109/anss.2007.31 dblp:conf/anss/LiuW07 fatcat:redolpwk3zb4nk2aejbzt2xd5q

A methodology for validation of microprocessors using symbolic simulation

Prabhat Mishra, Nikil Dutt, Narayanan Krishnamurthy, Magdy Abadir
2005 International Journal of Embedded Systems  
A significant bottleneck in the validation of processors is the lack of a golden reference model.  ...  The specification is used to generate the necessary reference models for processor validation using symbolic simulation.  ...  We would like to acknowledge the members of the ACES laboratory for their inputs.  ... 
doi:10.1504/ijes.2005.008805 fatcat:dhd3uvfm2nbynihv4jtk2arss4

Integrating Formal Verification into an Advanced Computer Architecture Course

M.N. Velev
2005 IEEE Transactions on Education  
This paper presents a sequence of three projects on design and formal verification of pipelined and superscalar processors: 1) a single-issue, five-stage DLX (an academic processor used widely for teaching  ...  The processors were designed and formally verified with a tool flow that was used to formally verify the M CORE processor at Motorola and detected bugs.  ...  Most importantly, this high-level definition of processors, coupled with certain modeling restrictions (Section III), allows the efficient formal verification of the pipelined designs.  ... 
doi:10.1109/te.2004.832880 fatcat:h7xexwcztbgp5gxjxr2ksfvjcy

Generating an Efficient Instruction Set Simulator from a Complete Property Suite

Ulrich Kühne, Sven Beyer, Christian Pichler
2009 2009 IEEE/IFIP International Symposium on Rapid System Prototyping  
We present an approach to automatically generate an instruction set simulator from a complete property suite, which can be used for the formal verification of the processor.  ...  Instruction set simulators can be used for the early development and testing of software for a processor before it is manufactured.  ...  Acknowledgment This research work was supported by the German Federal Ministry of Education and Research (BMBF) in the Project HERKULES under the contract number 01M3082.  ... 
doi:10.1109/rsp.2009.19 dblp:conf/rsp/KuhneBP09 fatcat:aiexq4e55vfjxbb4bgbzisw2qa

Profit or environment? A system dynamic model analysis of waste electrical and electronic equipment management system in China

Qinxin Guo, Enci Wang, Yongyou Nie, Junyi Shen
2018 Journal of Cleaner Production  
The simulations results suggest that the "WEEE processing fund" policy could improve the economic status of those receiving subsidies without losing the economic revenue from levies and improve the entire  ...  Keywords: Waste electrical and electronic equipment management; Waste electrical and electronic equipment processing fund; System dynamic model; Economic and environmental effects; China  ...  All the views expressed in this paper and any errors are the sole responsibility of the authors.  ... 
doi:10.1016/j.jclepro.2018.05.112 fatcat:5wpnyn7eh5f3jexf4arpvuznay

Retargetable generation of TLM bus interfaces for MP-SoC platforms

Andreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Tom Michiels, Achim Nohl, Tim Kogel
2005 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis - CODES+ISSS '05  
In order to meet flexibility, performance and energy efficiency constraints, future SoC (System-on-Chip) designs will contain an increasing number of heterogeneous processor cores combined with a complex  ...  For early system simulation, the adaptors are capable of bridging an abstraction gap by implementing a bus interface state machine.  ...  Communication models on multiple levels of abstraction for early processor integration have been proposed since a long time to overcome the simulation performance and modeling efficiency bottleneck [1  ... 
doi:10.1145/1084834.1084898 dblp:conf/codes/WieferinkLAMMNK05 fatcat:rjf6273bfbh7djndwp3baw5pke

A complexity theory of efficient parallel algorithms

Clyde P. Kruskal, Larry Rudolph, Marc Snir
1990 Theoretical Computer Science  
We show that a large number of parallel computation models are related via efficient simulations. if a polynomial reduction of the number of processors is allowed.  ...  These simulations are analyzed with respect to their efficiency and to the reducbon in the number of processors.  ...  We thank Martin Dietzfelbinger for informing us of his improvement to Lemma 4.19.  ... 
doi:10.1016/0304-3975(90)90192-k fatcat:txltfl7ymzekzihnn5veh2zkta

TLSim and EVC: a term-level symbolic simulator and an efficient decision procedure for the logic of equality with uninterpreted functions and memories

Miroslav N. Velev, Randal E. Bryant
2005 International Journal of Embedded Systems  
An earlier version of our tool flow was used to formally verify a model of the M • CORE processor at Motorola, and detected bugs.  ...  We present a tool flow for high-level design and formal verification of embedded processors.  ...  An efficient translation to CNF led to another two orders of magnitude speedup. The tool flow was used at Motorola to formally verify a model of the M • CORE processor and detected bugs.  ... 
doi:10.1504/ijes.2005.008815 fatcat:a7c2n3mtljdpbeujgwyhl2zq4i

Trace-driven rapid pipeline architecture evaluation scheme for ASIP design

Jun Kyoung Kim, Tag Gon Kim
2003 Proceedings of the 2003 conference on Asia South Pacific design automation - ASPDAC  
This paper proposes a rapid evaluation scheme of pipeline architecture using phase-accurate simulation with only delay model and trace.  ...  Branch target becomes available with trace generated by fast instruction set simulation. Fast verification time becomes possible because instruction set simulation is performed only once.  ...  Efficient design of a processor at this abstraction level requires formal definition of a processor, thus we introduced B-PASS(Basic Pipeline Architecture System Specification) formalism that defines a  ... 
doi:10.1145/1119772.1119798 dblp:conf/aspdac/KimK03 fatcat:qlrxfbfddbdxrbiubtne5imeye

Challenges in processor modeling and validation [Guest Editors' introduction]

P. Bose, T.M. Conte, T.M. Austin
1999 IEEE Micro  
The authors describe some newer trends in cosimulation and parallel simulation of the RTL model to tackle the simulation speed and efficiency bottlenecks.  ...  It is this model that is subjected to simulation-based architectural validation prior to actual tape-out of the processor.  ...  During 1992-94, he was assigned to IBM Austin as the lead performance engineer for the definition and evaluation of a processor core that evolved into the Power3 microprocessor.  ... 
doi:10.1109/mm.1999.768495 fatcat:jfxhc7zbsrhcrfdzr575xsnp2a

Player Simulation and General Adversary Structures in Perfect Multiparty Computation

Martin Hirt, Ueli Maurer
2000 Journal of Cryptology  
We formally define what it means to simulate a player by a multiparty protocol among a set of (new) players, and we derive the resilience of the new protocol as a function of the resiliences of the original  ...  Modeling this strategy would require to model (at least) the behavior of all internet users. 2 Synchronous means that the delay of messages is bounded by a constant. See [Can95] for more details.  ...  We are very grateful to Oded Goldreich for his detailed comments on the conference version of this paper [HM97] and for insisting on a sufficiently formal treatment, and to the anonymous referees for  ... 
doi:10.1007/s001459910003 fatcat:4kfgmjyga5fk7hbthpvqxhsqmu

Automatic Streaming Processing of XSLT Transformations Based on Tree Transducers [chapter]

Jana Dvořáková
2008 Studies in Computational Intelligence  
In this paper, we present the design of an automatic streaming processor of transformations specified in XSLT language.  ...  Unlike other similar systems, our processor guarantees bounds on the resource usage for the processing of a particular type of transformation.  ...  Each streaming model can simulate some restricted general model. The framework contains a simulation algorithm for each such pair streaming model → restricted general model.  ... 
doi:10.1007/978-3-540-74930-1_9 fatcat:fyd2p74ubbb4retdakqz3kivsu
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