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Efficient Realization of Strongly Indicating Function Blocks

P. Balasubramanian, D. A. Edwards
2008 2008 IEEE Computer Society Annual Symposium on VLSI  
This paper presents a technique for efficient gatelevel realization of strongly indicating function blocks.  ...  In this context, a novel design methodology for realizing non-regenerative logic as a function block, under the discipline of quasi-delayinsensitivity with four-phase handshaking and dualrail encoding,  ...  Acknowledgment The authors acknowledge the support of EPSRC, UK for the SEDATE project grant EP/D052238/1.  ... 
doi:10.1109/isvlsi.2008.103 dblp:conf/isvlsi/BalasubramanianE08 fatcat:lyw37jzb4zdvjhqlzjfesoll3m

Power, delay and area efficient self-timed multiplexer and demultiplexer designs

P. Balasubramanian, D.A. Edwards
2009 2009 4th International Conference on Design & Technology of Integrated Systems in Nanoscal Era  
Efficient gate level design methods for robust selftimed realization of arbitrary size multiplexer and demultiplexer function blocks, using elements of a commercial standard cell library are discussed  ...  While the optimal self-timed multiplexer implementations correspond to strong-indication, the optimal self-timed demultiplexer implementations pertain to weak-indication phenomenon.  ...  A function block can be classified as either strongly indicating or weakly indicating depending on how it behaves with respect to the handshaking transparency.  ... 
doi:10.1109/dtis.2009.4938050 fatcat:gdppd37kafcjvazlu2u2kjdlxm

An architecture of a dataflow single chip processor

S. Sakai, y. Yamaguchi, K. Hiraki, Y. Kodama, T. Yuba
1989 Proceedings of the 16th annual international symposium on Computer architecture - ISCA '89  
The distinctive features of it are: a strongly connected arc datafiow model; a direct matching scheme; a RISC-based design; a deadlock-free on-chip packet switch; and an integration of a packet-based circular  ...  This paper focuses on an architecture of the EMC-R.  ...  Hirosbi Kashiwagi, Deputy Director-General of the Electrotechnical Laboratory, Dr. Akio Tojo, Director of the Computer Science Division and Mr. Toshio Shimada.  ... 
doi:10.1145/74925.74931 dblp:conf/isca/SakaiYHKY89 fatcat:yghqs4k3wfec3mwhnuvxgqjamu

An architecture of a dataflow single chip processor

S. Sakai, y. Yamaguchi, K. Hiraki, Y. Kodama, T. Yuba
1989 SIGARCH Computer Architecture News  
The distinctive features of it are: a strongly connected arc datafiow model; a direct matching scheme; a RISC-based design; a deadlock-free on-chip packet switch; and an integration of a packet-based circular  ...  This paper focuses on an architecture of the EMC-R.  ...  Hirosbi Kashiwagi, Deputy Director-General of the Electrotechnical Laboratory, Dr. Akio Tojo, Director of the Computer Science Division and Mr. Toshio Shimada.  ... 
doi:10.1145/74926.74931 fatcat:w4anwfcudzfkzdsuq44yxmxeli

Machine Learning-Aided Numerical Linear Algebra: Convolutional Neural Networks for the Efficient Preconditioner Generation

Markus Goetz, Hartwig Anzt
2018 2018 IEEE/ACM 9th Workshop on Latest Advances in Scalable Algorithms for Large-Scale Systems (scalA)  
For test matrices where a natural block structure is complemented with a random distribution of nonzeros (noise), we show that a trained network succeeds in identifying strongly connected components with  ...  Segmenting a matrix into diagonal tiles of size 128 × 128, for each tile the sparsity pattern of an effective block-Jacobi preconditioner can be generated in less than a millisecond when using a production-line  ...  This indicates that supervariable blocking fails to detect the strongly coupled variables.  ... 
doi:10.1109/scala.2018.00010 fatcat:erohybz6irb27bwfgasglppb2y

A delay efficient robust self-timed full adder

P. Balasubramanian, D.A. Edwards
2008 2008 3rd International Design and Test Workshop  
The proposed adder satisfies Seitz's weak-indication specifications and exhibits reduced data path delay in comparison with other existing adders, which satisfy the property of indication.  ...  In terms of power and area, it is competitive to the best of other self-timed adders. I.  ...  This is possible as a valid combinatorial circuit cascade of strongly/weakly indicating function blocks is itself a strong/weak-indication function block [2] [8] .  ... 
doi:10.1109/idt.2008.4802482 fatcat:a35i36qfpnhknefcc3w7uw3qj4

Dual-Sum Single-Carry Self-Timed Adder Designs

P. Balasubramanian, D.A. Edwards
2009 2009 IEEE Computer Society Annual Symposium on VLSI  
This paper presents designs of self-timed dual-sum single-carry or dual-bit adder function blocks, constructed using commercially available synchronous library resources (standard cells) and validated  ...  The indication (completion) is either made implicit in the topology (local indication) or considerably isolated from the actual data path (a new variant of global indication) .  ...  Previous Work A function block (here, adder) is the asynchronous equivalent of a digital combinatorial logic circuit. Function blocks can be strongly indicating or weakly indicating [8] .  ... 
doi:10.1109/isvlsi.2009.13 dblp:conf/isvlsi/BalasubramanianE09 fatcat:cngu2dylabc67p23ol57oyesuy

Outline of a Methodic Realization of Construction Kits for Changeable Production Systems [chapter]

Michael Quade, David Jentsch, Egon Mueller
2014 IFIP Advances in Information and Communication Technology  
Combining building blocks according to requested functions for a product allows fulfilling many different customers' requirements cost efficiently with a limited amount of block entities.  ...  Additionally, regarding handling functions, the enabler universality strongly relates with the criteria.  ... 
doi:10.1007/978-3-662-44733-8_24 fatcat:a66df3qbabdafae3hgdsv4qxqi

Linear system matrices of rational transfer functions [article]

Froilán M. Dopico, María C. Quintana, Paul Van Dooren
2021 arXiv   pre-print
A strongly irreducible or minimal system matrix has the same structural elements as the rational matrix R(λ)= W(λ) + V(λ)T(λ)^-1U(λ), which is also known as the transfer function connected to the system  ...  In particular, we introduce the notion of strong minimality, and the corresponding conditions are shown to be sufficient for a polynomial system matrix to be strongly minimal.  ...  The first author was supported by "Ministerio de Economía, Industria y Competitividad (MINECO)" of Spain and "Fondo Europeo de Desarrollo Regional (FEDER)" of EU through grants MTM2015-65798-P and MTM2017  ... 
arXiv:1903.05016v2 fatcat:2thoyjttjjfdpimmb7x2yccisq

An Efficient Algorithm for Device Detection and Channel Estimation in Asynchronous IoT Systems [article]

Liang Liu, Ya-Feng Liu
2021 arXiv   pre-print
Then, a block coordinate descent algorithm is proposed to solve this problem globally, where the closed-form solution is available when updating each block of variables with the other blocks of variables  ...  This paper targets at two practical issues along this line that have not been addressed before: asynchronous transmission from uncoordinated users and efficient algorithms for real-time implementation  ...  We thus define the device activity indicator functions as follows: λn = 1, if device n is active, 0, otherwise, ∀n ∈ N . (1) Then, the set of active devices is defined by K = {n : λn = 1, ∀n ∈ N }.  ... 
arXiv:2010.09979v3 fatcat:dx5eectufbblllepb5tbx3sxfi

Erratum: A spectacularly reactive cathode

Josh Thomas
2004 Nature Materials  
Their studies of monodisperse colloidal solutions indicated that particles interacting strongly with multiple optical traps would be pushed to one side by an appropriately tuned array.  ...  By integrating a range of optically assembled, driven, and controlled components onto a single microfluidic chip, all-optical 'lab-on-a-microscope'systems could soon be realized (see Fig. 2 ).  ... 
doi:10.1038/nmat1036 fatcat:tr25kpjojbbuldxscnadc2i4be

Self-timed full adder designs based on hybrid input encoding

P. Balasubramanian, D.A. Edwards, C. Brej
2009 2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems  
A major part of this research is funded by EPSRC, UK through the SEDATE project grant EP/D052238/1. 978-1-4244-3339-1/09/$25.00 ©2009 IEEE Authorized licensed use limited to: The University of Manchester  ...  While one of the adder designs incorporates redundancy into the logic, the other design does not.  ...  Methods [3] and [6] can be used for function block realization (asynchronous equivalent of a synchronous combinatorial logic circuit), pertaining to strongly indicating or weakly indicating regimes  ... 
doi:10.1109/ddecs.2009.5012099 dblp:conf/ddecs/BalasubramanianEB09 fatcat:o7kl5q2oendf3gcsj5b45ixqyi

Enhancing Search Efficiency by Using Move Categorization Based on Game Progress in Amazons [chapter]

Yoshinori Higashiuchi, Reijer Grimbergen
2006 Lecture Notes in Computer Science  
Furthermore, it will be shown that the likelihood of move selection strongly depends upon the stage of the game.  ...  Therefore, improving the efficiency of the search is important for improving the playing strength of an Amazons program.  ...  These values strongly depend upon the evaluation function, so improvement of search speed can only be expected if the moves are ordered in the way the program 'likes them', i.e. that have a high probability  ... 
doi:10.1007/11922155_6 fatcat:2rp7xt7d2zenhkarld35sywqaa

Area Optimized Quasi Delay Insensitive Majority Voter for TMR Applications [article]

P Balasubramanian, D L Maskell, N E Mastorakis
2020 arXiv   pre-print
The corresponding outputs of the function blocks are majority voted using 3-input majority voters whose outputs define the outputs of a TMR realization.  ...  In a TMR realization, an original function block, which may be a circuit or a system, and two exact copies of the function block are used to successfully overcome any temporary fault or permanent failure  ...  It is observed in [15] that since the majority voter has only one dual rail primary output, a strongly indicating realization is necessary and weak indication or early output realizations are not suitable  ... 
arXiv:2008.05685v1 fatcat:26amuxdgjzdgvbtapperauv43y

Heterogeneously encoded dual-bit self-timed adder

P. Balasubramanian, D.A. Edwards
2009 2009 Ph.D. Research in Microelectronics and Electronics  
In comparison with dual-bit adders realized using other approaches, employing dual-rail encoding or heterogeneous encoding, the proposed design is found to be efficient in terms of delay, power consumption  ...  The design of a dual-bit adder is considered to illustrate the advantage of the heterogeneous encoding scheme. The proposed adder design satisfies Seitz's weak-indication timing constraints.  ...  Since a valid combinatorial circuit cascade of strong or weak-indication function blocks is itself a strongly or weakly indicating function block [3] , the individual adder modules could be cascaded to  ... 
doi:10.1109/rme.2009.5201301 fatcat:ca2ietp6brczvdko6ih6ewssum
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