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Efficient RLC Macromodels for Digital IC Interconnect [chapter]

Bogdan Tutuianu, Daksh Lehther, Madhulima Pandey, Ross Baldick
2000 IFIP Advances in Information and Communication Technology  
The paper presents a new method to synthesize macromodels for very large on-chip interconnection networks which can be simulated very efficiently with traditional SPICE-like simulators.  ...  Our method simplifies the task of simulating the interconnect by building a reduced order macromodel only for the subset of driving ports of the net.  ...  One such way to reduce the simulation time of very large circuit structures is to use reduced order macromodels for the RLC interconnect sections.  ... 
doi:10.1007/978-0-387-35498-9_26 fatcat:mfmenw3enbeelm3sosahfudaaa

Efficient Delay and Crosstalk Modeling of RLC Interconnects Using Delay Algebraic Equations

Sourajeet Roy, Anestis Dounavis
2011 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
This paper presents a delay and crosstalk noise model for coupled resistance-inductance-capacitance (RLC) on-chip interconnects.  ...  Index Terms-Aggressor line, crosstalk, delay, inductance, interconnects, system analysis and design, transmission line theory, victim line.  ...  This fact will be used to derive an efficient delay and crosstalk model for coupled RLC interconnects. III.  ... 
doi:10.1109/tvlsi.2009.2032288 fatcat:sy2bq3etljaepaf44hzyzktply

Passive Multiport RC Model Extraction for Through Silicon Via Interconnects in 3-D ICs

A. Ege Engin
2014 IEEE transactions on electromagnetic compatibility (Print)  
This paper describes a methodology to extract parasitic RC models from such simulation data for interconnects in a 3-D IC. Index Terms-Macromodeling, passivity, RC model, through silicon vias (TSVs).  ...  Parasitic RC behavior of VLSI interconnects has been the major bottleneck in terms of latency and power consumption of ICs.  ...  This approach for the first time solves the problem of efficiently generating passive macromodels for 3-D IC interconnects. A one-port solution for this problem has been presented in [19] .  ... 
doi:10.1109/temc.2013.2295049 fatcat:ofp46ierc5az7hl4micvl44kia

Behavioral Models of Input/Output Buffers Including Core Noise Coupling

I.S. Stievano, C. Siviero, F.G. Canavero, I.A. Maio
2008 2008 12th IEEE Workshop on Signal Propagation on Interconnects  
Submodels efficient models of the ports of the active components, as the iH and it can be obtained from either simplified equivalent Input/Output (I/O) buffers of digital Integrated Circuits (ICs) circuit  ...  Additionally, macromodels obtained by this 30% of the nominal supply voltage values. parametric approach remain almost as efficient as macromodels based on IBIS data and can be easily included in Enhanced  ... 
doi:10.1109/spi.2008.4558343 fatcat:6pzre2owgbccxibtqchg2lxrq4

SuPREME: substrate and power-delivery reluctance-enhanced macromodel evaluation

Tsung-Hao Chen, C. Luk, C.C.-P. Chen
2003 ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486)  
In this paper, we propose a novel and efficient reluetanc-based passive model order reduction technique to serve these tasks Our work, SuPREME(&bstrate and -Power-delivery &luctance-Enhanced Macromodel  ...  However, the increasing design complexity meat-tremendous challenges for chiplevel powerdelivery substrate co-analysis.  ...  [I][Z] Unfortunately, the rising clock frequency for both analog and digital circuits and the adoption of low-k and high conductivity interconnects and high conductivity substrates require consideration  ... 
doi:10.1109/iccad.2003.159766 fatcat:j35gzvwib5fajam35om4yv5wzi

Addressing substrate coupling in mixed-mode ICs: simulation and power distribution synthesis

B.R. Stanisic, N.K. Verghese, R.A. Rutenbar, L.R. Carley, D.J. Allstot
1994 IEEE Journal of Solid-State Circuits  
For synthesis, a coarse substrate mesh, and interconnect models are used to couple linear macromodels of circuit functional blocks.  ...  For simulation, a macromodel of the fine substrate mesh is formulated and a modified version of SPICE3 is used to simulate the electrical circuit coupled with the macromodel.  ...  For each power bus segment, we generate a parasitic RC 7r model. For chip-package interconnect, we estimate wire bond inductance.  ... 
doi:10.1109/4.278344 fatcat:qvdcxh5k4faczoor4zbestuc6i

Addressing Substrate Coupling in MixedMode IC's: Simulation and Power Distribution Synthesis [chapter]

2009 Computer-Aided Design of Analog Integrated Circuits and Systems  
For synthesis, a coarse substrate mesh, and interconnect models are used to couple linear macromodels of circuit functional blocks.  ...  For simulation, a macromodel of the fine substrate mesh is formulated and a modified version of SPICE3 is used to simulate the electrical circuit coupled with the macromodel.  ...  For each power bus segment, we generate a parasitic RC 7r model. For chip-package interconnect, we estimate wire bond inductance.  ... 
doi:10.1109/9780470544310.ch39 fatcat:sm7dia4ouvekxiy2gxgtdild6a

Present and future of I/O-buffer behavioral macromodels

Signorini, Siviero, Telescu, Stievano
2016 IEEE Electromagnetic Compatibility Magazine  
Known as behavioral models, surrogate models or macromodels, these computationally efficient equivalents have become a de-facto industry standard in SI/PI simulations.  ...  His recent activities include the behavioral modeling of digital ICs, transmission lines and PLC channels, the modeling and simulation of switching converters and the development of stochastic methods  ...  I/O-Buffer macromodeling concept The top panel of Fig. 1 shows the typical structure of a single-ended output buffer that interfaces the internal IC core with the external interconnects.  ... 
doi:10.1109/memc.0.7764256 fatcat:rbxjup3vanaghn34pdplojlrwu

Behavioral Modeling of Flash Memories [chapter]

Igor S., Ivan A., Flavio G.
2011 Flash Memories  
Introduction Over the past ten years, the interest in the development of accurate and efficient models of high-speed digital integrated circuits (ICs) has grown.  ...  network of a digital IC.  ... 
doi:10.5772/21381 fatcat:nvfdzcnm5vdcrkzlsz3xla5iaq

Thermal Via Allocation for 3D ICs Considering Temporally and Spatially Variant Thermal Power

Hao Yu, Yiyu Shi, Lei He, Tanay Karnik
2006 ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design  
ACKNOWLEDGMENT The authors would like to thank the reviewers for their insightful comments to make this paper better.  ...  Similar to the macromodeling for the interconnect network, the moment-matching based model order reduction can be used to obtain a 3-D IC thermal-macromodel with compact-sized , which not only has a smaller  ...  circuits (ICs) is effective to improve the interconnect performance and increase the transistor packing density.  ... 
doi:10.1109/lpe.2006.4271828 fatcat:dyqbw3ralzg3pk2rdt6nh7b5c4

Thermal Via Allocation for 3-D ICs Considering Temporally and Spatially Variant Thermal Power

Hao Yu, Yiyu Shi, Lei He, Tanay Karnik
2008 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
ACKNOWLEDGMENT The authors would like to thank the reviewers for their insightful comments to make this paper better.  ...  Similar to the macromodeling for the interconnect network, the moment-matching based model order reduction can be used to obtain a 3-D IC thermal-macromodel with compact-sized , which not only has a smaller  ...  circuits (ICs) is effective to improve the interconnect performance and increase the transistor packing density.  ... 
doi:10.1109/tvlsi.2008.2001297 fatcat:j6i7mq5zizcljmd36u77rcmcrq

Automated nonlinear macromodelling of output buffers for high-speed digital applications

Ning Dong, J. Roychowdhury
2005 Proceedings. 42nd Design Automation Conference, 2005.  
We demonstrate the technique by automatically extracting macromodels for two typical digital drivers.  ...  Good nonlinear macromodels of such drivers are essential for fast signal-integrity and timing analysis in high-speed digital design.  ...  Finally, the generated macromodel is represented as an equivalent sub-circuit, which is implemented in SPICE and simulated with load interconnects.  ... 
doi:10.1109/dac.2005.193772 fatcat:v3j3la62hfgh3h26pbojzuiqq4

Automated nonlinear Macromodelling of output buffers for high-speed digital applications

Ning Dong, Jaijeet Roychowdhury
2005 Proceedings of the 42nd annual conference on Design automation - DAC '05  
We demonstrate the technique by automatically extracting macromodels for two typical digital drivers.  ...  Good nonlinear macromodels of such drivers are essential for fast signal-integrity and timing analysis in high-speed digital design.  ...  Finally, the generated macromodel is represented as an equivalent sub-circuit, which is implemented in SPICE and simulated with load interconnects.  ... 
doi:10.1145/1065579.1065598 dblp:conf/dac/DongR05 fatcat:btsnws4ds5dw3pggoztonpefoa

Modeling and analysis of power distribution networks for gigabit applications

Jinwoo Choi, Sung-Hwan Min, Joong-Ho Kim, M. Swaminathan, W.W. Beyene, Xingchao Chuck Yuan
2003 IEEE Transactions on Mobile Computing  
Finally, the macromodel of the planes, transmission lines, and nonlinear drivers have been simulated in standard SPICE-based circuit simulators for computing power supply noise.  ...  In this paper, a hybrid method has been applied for analysis which consists of the Transmission Matrix Method (TMM) in the frequency domain and Macromodeling method in the time domain.  ...  Swaminathan's research interests are in design, electromagnetic modeling, circuit modeling, characterization and testing of high frequency digital, and mixed signal ICs and packages.  ... 
doi:10.1109/tmc.2003.1255645 fatcat:yvk4gpbvmzgb7fps52kdrwktjq

On-chip inductance cons and pros

Y.I. Ismail
2002 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
Among the undesirable effects of on-chip inductance are higher interconnect coupling noise and substrate coupling, challenges for accurate extraction, the required modifications of the infrastructure of  ...  Among the desirable effects is lower power consumption, less need for repeaters, faster signal rise time, and less delay uncertainty.  ...  Thus, the global wires connecting modules across an IC have increased in length.  ... 
doi:10.1109/tvlsi.2002.808445 fatcat:2jllrugahveuzhossis5ym2viq
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