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Efficient memory integrity verification and encryption for secure processors

G.E. Suh, D. Clarke, B. Gasend, M. van Dijk, S. Devadas
22nd Digital Avionics Systems Conference. Proceedings (Cat. No.03CH37449)  
This paper proposes new hardware mechanisms for memory integrity verification and encryption, which are two key primitives required in singlechip secure processors.  ...  Secure processors enable new sets of applications such as commercial grid computing, software copy-protection, and secure mobile agents by providing security from both physical and software attacks.  ...  The assumed model and how integrity verification and encryption are used in secure processors is presented in Section 2.  ... 
doi:10.1109/micro.2003.1253207 dblp:conf/micro/SuhCGDD03 fatcat:wnxhqmpq3bg4vlnjogjil73jpa

AEGIS

G. Edward Suh, Dwaine Clarke, Blaise Gassend, Marten van Dijk, Srinivas Devadas
2014 25th Anniversary International Conference on Supercomputing Anniversary Volume -  
We describe the architecture for a single-chip aegis processor which can be used to build computing systems secure against both physical and software attacks.  ...  Our architecture assumes that all components external to the processor, such as memory, are untrusted. We show two different implementations.  ...  We would also like to thank Ron Rivest and Krste Asanovic for many constructive comments, as well as all the members of our group who helped proof-read this paper.  ... 
doi:10.1145/2591635.2667184 fatcat:vsxhymcelfbr3pjbxnt2upkw44

AEGIS

G. Edward Suh, Dwaine Clarke, Blaise Gassend, Marten van Dijk, Srinivas Devadas
2003 Proceedings of the 17th annual international conference on Supercomputing - ICS '03  
We describe the architecture for a single-chip aegis processor which can be used to build computing systems secure against both physical and software attacks.  ...  Our architecture assumes that all components external to the processor, such as memory, are untrusted. We show two different implementations.  ...  We would also like to thank Ron Rivest and Krste Asanovic for many constructive comments, as well as all the members of our group who helped proof-read this paper.  ... 
doi:10.1145/782814.782838 dblp:conf/ics/SuhCGDD03 fatcat:qxgo3jshfng5vkowxbifl7go44

A low overhead hardware technique for software integrity and confidentiality

Austin Rogers, Milena Milenkovic, Aleksandar Milenkovic
2007 2007 25th International Conference on Computer Design  
In this paper we describe an efficient hardware mechanism that protects software integrity and guarantees software confidentiality.  ...  Software integrity and confidentiality play a central role in making embedded computer systems resilient to various malicious actions, such as software attacks; probing and tampering with buses, memory  ...  for memory integrity verification [24] , a XOM-like architecture with fast one-time-pad encryption [3] , an architecture for runtime verification of instruction block signatures [4] , and a hardware  ... 
doi:10.1109/iccd.2007.4601889 dblp:conf/iccd/RogersMM07 fatcat:cgytoktd4zfu7lvplhtbpzzdou

CryptoPage: An Efficient Secure Architecture with Memory Encryption, Integrity and Information Leakage Protection

Guillaume Duc, Ronan Keryell
2006 Proceedings of the Computer Security Applications Conference  
Several secure computing hardware architectures using memory encryption and memory integrity checkers have been proposed during the past few years to provide applications with a tamper resistant environment  ...  We propose the CRYPTOPAGE architecture which implements memory encryption, memory integrity protection checking and information leakage protection together with a low performance penalty (3 % slowdown  ...  The authors wish to thank Jacques Stern for his valuable comments on this project, Sylvain Guilley and Renaud Pacalet for their insightful discussions in the GET-TCP project.  ... 
doi:10.1109/acsac.2006.21 dblp:conf/acsac/DucK06 fatcat:f4mt32yzfnfi7fecobzlqitsj4

Using Address Independent Seed Encryption and Bonsai Merkle Trees to Make Secure Processors OS- and Performance-Friendly

Brian Rogers, Siddhartha Chhabra, Milos Prvulovic, Yan Solihin
2007 Microarchitecture (MICRO), Proceedings of the Annual International Symposium on  
In particular, researchers have proposed designs for secure processors which utilize hardware-based memory encryption and integrity verification to protect the privacy and integrity of computation even  ...  memory integrity verification technique, to eliminate these system and performance issues associated with prior counter-mode memory encryption and Merkle Tree integrity verification schemes.  ...  Several different approaches have previously been studied for memory integrity verification in secure processors.  ... 
doi:10.1109/micro.2007.4408255 fatcat:glnpa7ifhjfvbecicr7e3jbgje

Using Address Independent Seed Encryption and Bonsai Merkle Trees to Make Secure Processors OS- and Performance-Friendly

Brian Rogers, Siddhartha Chhabra, Milos Prvulovic, Yan Solihin
2007 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007)  
In particular, researchers have proposed designs for secure processors which utilize hardware-based memory encryption and integrity verification to protect the privacy and integrity of computation even  ...  memory integrity verification technique, to eliminate these system and performance issues associated with prior counter-mode memory encryption and Merkle Tree integrity verification schemes.  ...  Several different approaches have previously been studied for memory integrity verification in secure processors.  ... 
doi:10.1109/micro.2007.16 dblp:conf/micro/RogersCPS07 fatcat:qxiadelsg5dkzpji35tgql7f7e

Accelerating memory decryption and authentication with frequent value prediction

Weidong Shi, Hsien-Hsin S. Lee
2007 Proceedings of the 4th international conference on Computing frontiers - CF '07  
Without sacrificing security, frequent value ciphertext speculation can speed up memory decryption or MAC integrity verification by speculatively encrypting predictable memory values and comparing the  ...  A number of recent secure processor designs have used memory block encryption and authentication to protect un-trusted external memory.  ...  BACKGROUND OF HARDWARE BASED MEMORY ENCRYPTION This section discusses the role of memory encryption and integrity verification for secure processor design.  ... 
doi:10.1145/1242531.1242539 dblp:conf/cf/ShiL07 fatcat:z54jp3wr3nbs3ckzxyptwcdyme

Effective implementation of the cell broadband engine™ isolation loader

Masana Murase, Kanna Shimizu, Wilfred Plouffe, Masaharu Sakamoto
2009 Proceedings of the 16th ACM conference on Computer and communications security - CCS '09  
Our isolation loader is a key component in realizing secure application boot and encrypted application execution.  ...  The load overhead of this loader including application fetch, validation (RSA-2048/SHA-1), and decryption (RSA-2048 and AES) is less than 50 milliseconds on the 2.8 GHz IBM Pow-erXCell 8i processor.  ...  ACKNOWLEDGMENTS The authors would like to thank the management team, development team, the researchers, and the architects for  ... 
doi:10.1145/1653662.1653699 dblp:conf/ccs/MuraseSPS09 fatcat:f6tlqpqazjbjbo6pzihmuq3jbm

PoisonIvy: Safe speculation for secure memory

Tamara Silbergleit Lehman, Andrew D. Hilton, Benjamin C. Lee
2016 2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)  
Encryption and integrity trees guard against physical attacks, but harm performance.  ...  PoisonIvy reduces performance overheads from 40% to 20% for memory intensive workloads and down to 1.8%, on average.  ...  CONCLUSIONS A trusted processor employs encryption and integrity trees to guard against physical attacks.  ... 
doi:10.1109/micro.2016.7783741 dblp:conf/micro/LehmanHL16 fatcat:vsdc4murjrazxnqefzuko3a3bu

Making secure processors OS- and performance-friendly

Siddhartha Chhabra, Brian Rogers, Yan Solihin, Milos Prvulovic
2009 ACM Transactions on Architecture and Code Optimization (TACO)  
In particular, researchers have proposed designs for secure processors which utilize hardware-based memory encryption and integrity verification to protect the privacy and integrity of computation even  ...  memory integrity verification technique, to eliminate these system and performance issues associated with prior counter-mode memory encryption and Merkle Tree integrity verification schemes.  ...  Several different approaches have previously been studied for memory integrity verification in secure processors.  ... 
doi:10.1145/1498690.1498691 fatcat:btyvqqoplvaxfk3mg2njsh4ipy

Security extensions for integrity and confidentiality in embedded processors

Austin Rogers, Aleksandar Milenković
2009 Microprocessors and microsystems  
These extensions ensure the integrity and confidentiality of both instructions and data, introducing low performance overhead (1.86% for instructions and 14.9% for data).  ...  We propose several cost-effective architectural extensions suitable for mid-range to high-end embedded processors.  ...  Main memory is assumed to be insecure, so all data entering and leaving the processor while it is running in secure mode is encrypted.  ... 
doi:10.1016/j.micpro.2009.06.002 fatcat:55xe2pry2feabgjkekktggee6u

A Trusted Computing Architecture of Embedded System Based on Improved TPM

Xiaosheng Wang, Gaochao Xu, Yongfei Han, Yanchun Yang, Bing Xu, Yinong Chen
2017 MATEC Web of Conferences  
Experiments show that the trusted architecture of the embedded system based on the improved TPM is efficient, reliable and secure.  ...  control, active defense, high-speed encryption/decryption and other function through its internal bus arbitration module and symmetric and asymmetric cryptographic engines to effectively protect the security  ...  to read the external memory data for reliability verification, there are both the ARM processor and the eTPCM need to access the external memory, so the external memory bus needs to be arbitrated. (3)  ... 
doi:10.1051/matecconf/201713900151 fatcat:6puwrrwx2vfblh5ysvedmk54bu

Improving virus protection with an efficient secure architecture with memory encryption, integrity and information leakage protection

Guillaume Duc, Ronan Keryell
2007 Journal in Computer Virology  
Several secure computing hardware architectures using memory encryption and memory integrity checkers have been proposed during the past few years to provide applications with a tamper resistant environment  ...  We propose the CryptoPage architecture which implements memory encryption, memory integrity protection checking and information leakage protection together with a low performance penalty (3% slowdown on  ...  The authors wish to thank Jacques Stern for his valuable comments on this project, Sylvain Guilley and Renaud Pacalet for their insightful discussions in the get-tcp project.  ... 
doi:10.1007/s11416-007-0062-0 fatcat:ydaiqqpiabfofdgraho43q6vii

Aegis: A single-chip secure processor

G. Suh, Charles O'Donnell, Srinivas Devadas
2007 IEEE Design & Test of Computers  
Memory encryption and integrity verification mechanisms guarantee the privacy and the integrity of off-chip memory content, respectively.  ...  AEGIS, with its off-chip protection mechanisms, is slower than traditional processors by 26% on average for large applications and by a few percent for embedded applications.  ...  integrity verification and encryption.  ... 
doi:10.1109/mdt.2007.4343587 fatcat:qzwlnqrklvat5kgjzia7yed47q
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