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Efficient Mapping of Addition Recurrence Algorithms in CMOS

B.R. Zeydel, T.T.J.H. Kluter, V.G. Oklobdzija
17th IEEE Symposium on Computer Arithmetic (ARITH'05)  
Efficient adder design requires proper selection of a recurrence algorithm and its realization.  ...  Each of the algorithms: Weinberger's, Ling's and Doran's were analyzed for its flexibility in representation and suitability for realization in CMOS.  ...  Several realization techniques have been developed to efficiently map recurrence algorithms to CMOS technology under these constraints [14] .  ... 
doi:10.1109/arith.2005.19 dblp:conf/arith/ZeydelKO05 fatcat:7sbl7z2kwvhfxlmnk2wdmdsgsa

Design of Radix-4 SRT Dividers in 65 Nanometer CMOS Technology

Tung Pham, Earl Jr. Swartzlander
2006 IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06)  
In the CMOS technologies of the recent past where minimizing the die area was crucial, radix-4 minimally redundant SRT dividers were widely used because they only require simple multiples of divisor.  ...  To illustrate this concept of trading extra hardware for improved power and speed and a simpler implementation, a radix-4 maximally redundant divider is designed and implemented in 65 nm CMOS technology  ...  These two metrics in addition to the duty cycle are used to evaluate the energy efficiency of the designs.  ... 
doi:10.1109/asap.2006.26 dblp:conf/asap/PhamS06 fatcat:3gmbtfzi45bipfictglbhhzhrq

Video analytics using beyond CMOS devices

Vijaykrishnan Narayanan, Suman Datta, Gert Cauwenberghs, Don Chiarulli, Steve Levitan, Philip Wong
2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2014  
The design of such a system needs advances in multiple disciplines.  ...  This paper focuses on advances needed in the computational fabric and provides an overview of a newgenre of architectures inspired by advances in both the understanding of the visual cortex and the emergence  ...  This architecture is amenable to mapping various vision processing algorithms based on spiked neural networks.  ... 
doi:10.7873/date.2014.357 dblp:conf/date/NarayananDCCLW14 fatcat:b2ynwr3qzfdhlbkemnw2jtptra

Hardware Implementation of Deep Network Accelerators Towards Healthcare and Biomedical Applications

Mostafa Rahimiazghadi, Corey Lammie, Jason Kamranr Eshraghian, Melika Payvand, Elisa Donati, Bernabe Linares-Barranco, Giacomo Indiveri
2020 IEEE Transactions on Biomedical Circuits and Systems  
Oxide Semiconductor (CMOS) technology can be used to develop efficient DL accelerators to solve a wide variety of diagnostic, pattern recognition, and signal processing problems in healthcare.  ...  In addition, we benchmark various hardware platforms by performing a biomedical electromyography (EMG) signal processing task and drawing comparisons among them in terms of inference delay and energy.  ...  In addition, there are many other approaches commonly used to make neural network implementations more efficient.  ... 
doi:10.1109/tbcas.2020.3036081 pmid:33156792 fatcat:rjwfjd7vmvglpk762mqeyiteqq

Hardware Implementation of Deep Network Accelerators Towards Healthcare and Biomedical Applications [article]

Mostafa Rahimi Azghadi, Corey Lammie, Jason K. Eshraghian, Melika Payvand, Elisa Donati, Bernabe Linares-Barranco, Giacomo Indiveri
2020 arXiv   pre-print
Oxide Semiconductor (CMOS) technology can be used to develop efficient DL accelerators to solve a wide variety of diagnostic, pattern recognition, and signal processing problems in healthcare.  ...  In addition, we benchmark various hardware platforms by performing a biomedical electromyography (EMG) signal processing task and drawing comparisons among them in terms of inference delay and energy.  ...  In addition, an update module that updates network weights based on an algorithm such as SGD is required, which is usually implemented in software.  ... 
arXiv:2007.05657v1 fatcat:amqutl3suvgq5nygna4ef36usy

Towards Real-Time In-Implant Epileptic Seizure Prediction

Joseph N. Y. Aziz, Rafal Karakiewicz, Roman Genov, Berj L. Bardakjian, Miron Derchansky, Peter L. Carlen
2006 2006 International Conference of the IEEE Engineering in Medicine and Biology Society  
The wavelet-based artificial neural network predicts the onsets of seizure up to two minutes before their occurrence in an in-vitro epilepsy model using a mouse hippocampal brain slice with recurrent spontaneous  ...  The neural interface and the spectral analysis processor have been prototyped in a 0.35 μm CMOS technology with experimental results are presented.  ...  This represents an energy-efficient and cost-effective solution for implementations of very computationally intensive learning algorithms, such as epileptic seizure prediction algorithms in real time,  ... 
doi:10.1109/iembs.2006.259737 pmid:17947144 fatcat:fx43fjuquzgwtpeswewfxsjzte

RNNFast: An Accelerator for Recurrent Neural Networks Using Domain Wall Memory [article]

Mohammad Hossein Samavatian, Anys Bacha, Li Zhou, Radu Teodorescu
2018 arXiv   pre-print
RNNFast is very efficient and highly scalable, with flexible mapping of logical neurons to RNN hardware blocks.  ...  Recurrent Neural Networks (RNNs) are an important class of neural networks designed to retain and incorporate context into current decisions.  ...  based on racetrack chains. • Demonstrates that DWM is very well suited for efficient acceleration of recurrent neural networks.  ... 
arXiv:1812.07609v1 fatcat:2x2b3iqahrffrma5lc2ut2ivi4

Towards Real-Time In-Implant Epileptic Seizure Prediction

Joseph N. Y. Aziz, Rafal Karakiewicz, Roman Genov, Berj L. Bardakjian, Miron Derchansky, Peter L. Carlen
2006 IEEE Engineering in Medicine and Biology Society. Conference Proceedings  
The wavelet-based artificial neural network predicts the onsets of seizure up to two minutes before their occurrence in an in-vitro epilepsy model using a mouse hippocampal brain slice with recurrent spontaneous  ...  The neural interface and the spectral analysis processor have been prototyped in a 0.35 μm CMOS technology with experimental results are presented.  ...  This represents an energy-efficient and cost-effective solution for implementations of very computationally intensive learning algorithms, such as epileptic seizure prediction algorithms in real time,  ... 
doi:10.1109/iembs.2006.4398694 fatcat:iqocovls3vb4vlndz5o6zsrhmu

Design Optimization of Power and Area of Two-Stage CMOS Operational Amplifier Utilizing Chaos Grey Wolf Technique

Telugu Maddileti, Govindarajulu Salendra, Chandra Mohan
2020 International Journal of Advanced Computer Science and Applications  
In this study, the design of a two-stage CMOS Differential Amplifier applying the nature-inspired Grey Wolf Algorithm for optimizing the area and power is utilized.  ...  Functionality in terms of rapidity, dissipation of power, etc. are strongly influenced by the dimensions of transistors in many CMOS Integrated Circuits.  ...  It can be thus inferred that the recurrent firing of the neuron and regular accomplishment of the local search algorithm is circumscribed.  ... 
doi:10.14569/ijacsa.2020.0110760 fatcat:sasdsqd4qrbtnn37ih5paw76gq

Complex Learning in Bio-plausible Memristive Networks

Lei Deng, Guoqi Li, Ning Deng, Dong Wang, Ziyang Zhang, Wei He, Huanglong Li, Jing Pei, Luping Shi
2015 Scientific Reports  
However, the lack of both internal dynamics in the previous feedforward memristive networks and efficient learning algorithms in recurrent networks, fundamentally limits the learning ability of existing  ...  In this context, various CMOS hardware-based neuromorphic systems have been developed 5-9 .  ...  Acknowledgements Financial supports from the National Natural Science Foundation of China (No. 61475080) and the Study of Brain-Inspired Computing System of Tsinghua University (No. 20141080934) are acknowledged  ... 
doi:10.1038/srep10684 pmid:26090862 pmcid:PMC4473596 fatcat:mhj4iza3uzeillb7ffku6hogse

Cyclic reservoir neural network circuit for 3D IC implementation

Keisuke Fukuda, Yoshihiko Horio, Takemori Orima, Koji Kiyoyama, Mitsumasa Koyanagi
2021 Nonlinear Theory and Its Applications IEICE  
Furthermore, a simple learning algorithm only in the output layer is sufficient for training the entire network. Therefore, its efficient hardware implementation is highly expected.  ...  We designed and fabricated a prototype IC chip of the proposed circuit with a TSMC 180 nm CMOS semiconductor process.  ...  This work is supported by VLSI Design and Education Center (VDEC), the University of Tokyo in collaboration with Cadence Design Systems, Inc., for IC design tools.  ... 
doi:10.1587/nolta.12.309 fatcat:xxrtdt5ncjflnhkd3vhdsbsqlq

Memristors – from In-memory computing, Deep Learning Acceleration, Spiking Neural Networks, to the Future of Neuromorphic and Bio-inspired Computing [article]

Adnan Mehonic, Abu Sebastian, Bipin Rajendran, Osvaldo Simeone, Eleni Vasilaki, Anthony J. Kenyon
2020 arXiv   pre-print
This paper reviews the case for a novel beyond CMOS hardware technology, memristors, as a potential solution for the implementation of power-efficient in-memory computing, deep learning accelerators, and  ...  These successes have been mostly supported by three factors: availability of vast amounts of data, continuous growth in computing power, and algorithmic innovations.  ...  If recurrences exist and are required, there must be a way to efficiently train such structures.  ... 
arXiv:2004.14942v1 fatcat:b52hrjk365f2tabarxg4zfys44

Quantum neuromorphic hardware for quantum artificial intelligence

Enrico Prati
2017 Journal of Physics, Conference Series  
Here I review the convergence between the two fields towards implementation of advanced quantum algorithms, including quantum deep learning.  ...  The development of machine learning methods based on deep learning boosted the field of artificial intelligence towards unprecedented achievements and application in several fields.  ...  A prominent example of deep learning network designed on CMOS silicon hardware at circuit level has been provided in [19] .  ... 
doi:10.1088/1742-6596/880/1/012018 fatcat:ivfn67ojgngixgfwvwiq4eih2e

Memristors—From In‐Memory Computing, Deep Learning Acceleration, and Spiking Neural Networks to the Future of Neuromorphic and Bio‐Inspired Computing

Adnan Mehonic, Abu Sebastian, Bipin Rajendran, Osvaldo Simeone, Eleni Vasilaki, Anthony J. Kenyon
2020 Advanced Intelligent Systems  
If recurrences exist and are required, there must be a way to efficiently train such structures.  ...  It is unlikely that current digital CMOS transistor technology can be optimized for the implementation of much more dynamic and adaptive systems in an efficient way.  ... 
doi:10.1002/aisy.202000085 fatcat:3ov6ahzlvjhlbn7bvvfnzmf26e

Loop acceleration by cluster-based CGRA

Li Zhou, Hengzhu Liu, Jianfeng Zhang
2013 IEICE Electronics Express  
The reconfigurable clusters in this CGRA are composed of generic processing elements (PE) and shared PEs. The local connectivity of a cluster is utilized in the proposed mapping heuristic.  ...  Routing in the PE array is avoided because data transmission is within a cluster or between adjacent clusters in the heuristic.  ...  The loop kernel is successfully mapped in II 2 = 2 without additional route node. The nth and the n + 1th iteration, as well as the nth and the n + 2th iteration, can be executed in parallel.  ... 
doi:10.1587/elex.10.20130506 fatcat:754bfrwudjan5af7whhfqsiovy
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