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Modeling and Evaluation of Chip-to-Chip Scale Silicon Photonic Networks

Robert Hendry, Dessislava Nikolova, Sebastien Rumley, Keren Bergman
2014 2014 IEEE 22nd Annual Symposium on High-Performance Interconnects  
In this paper, we perform comprehensive design exploration of inter-chip photonic links and networking architectures.  ...  To conduct this exploration, we introduce a modeling methodology that captures not only the physical layer characteristics in terms of link capacity and energy efficiency but also the network utilization  ...  ACKNOWLEDGEMENTS We gratefully acknowledge support for this work under MIT Lincoln Laboratory PO MIT-7000135026 and the U.S. Department of Energy Sandia National Laboratories PO 1426332.  ... 
doi:10.1109/hoti.2014.14 dblp:conf/hoti/HendryNRB14 fatcat:n3rgzx5vlzfl7ia54vvctxt7tu

Reconfigurable on-chip communication link for efficient communication

Beulah Hemalatha S, Vigneswaran T
2018 International Journal of Engineering & Technology  
Application specific reconfiguration of On-chip communication link is a fast growing research area in system on chip (SoC) based system design.  ...  Here, in this paper genetic algorithm based On-chip communication link reconfiguration is presented.  ...  System model The On-chip communication link consist of reconfigurable serial and parallel link .Optimal packet size, selection of serial and parallel link, clock rate and parallel link size are the parameters  ... 
doi:10.14419/ijet.v7i2.9760 fatcat:w6cety6fyzdzrma3bla5udf3wu

Analysis and Implementation of Practical, Cost-Effective Networks on Chips

Se-Joong Lee, Kangmin Lee, Hoi-Jun Yoo
2005 IEEE Design & Test of Computers  
on a single chip will keep increasing. 3 Use of a high-speed clock and the multicore architecture requires an on-chip bus architecture to evolve into a network architecture.  ...  Design parameters for on-chip serialization.  ...  His research interests include the theory, architecture, and VLSI design of highspeed network switches and on-chip interconnection networks.  ... 
doi:10.1109/mdt.2005.103 fatcat:gp6msxhvqbg47fvpqt5fg7einm

A micro-network on chip with 10-Gb/s transmission link

Wei-Chang Liu, Chih-Hsien Lin, Shyh-Jye Jou, Hung-Wen Lu, Chau-Chin Su, Kai-Wei Hong, Kuo-Hsing Cheng, Shyue-Wen Yang, Ming-Hwa Sheu
2009 2009 IEEE Asian Solid-State Circuits Conference  
In this paper, a micro-network on chip (MNoC) with 10-Gb/s transmission link is proposed.  ...  The core area of this chip is 990 m*1600 m and the power consumption is 155mW (60mW for micro-switches and 95mW for 10-Gb/s data transceiver) at 1.2V supply voltage with 10-Gb/s transmission data rate.  ...  ACKNOWLEDGMENT The authors thank National Chip Implementation Center (CIC), Taiwan, for technology supports and chip implementation.  ... 
doi:10.1109/asscc.2009.5357256 fatcat:4mt77oez5bbihizbogjj43qque

An area-efficient dynamically reconfigurable Spatial Division Multiplexing network-on-chip with static throughput guarantee

Zhiyao Joseph Yang, Akash Kumar, Yajun Ha
2010 2010 International Conference on Field-Programmable Technology  
With an increasing trend to implement Network-on-Chip (NoC)-based Multi-Processor Systems-on-Chips (MPSoCs), NoCs need to have guaranteed services and be dynamically reconfigurable.  ...  We replaced area consuming 32-bit to M-bit serializers with 32-bit to 1-bit serializers in the network interface and incur almost no loss in performance.  ...  ACKNOWLEDGMENT The authors would like to thank Mr Shakith Fernando for his assistance in the development of the MPSoC platform.  ... 
doi:10.1109/fpt.2010.5681443 dblp:conf/fpt/YangKH10 fatcat:zm3ijbnpk5gwpelnuujwdxrhvu

Solutions for Real Chip Implementation Issues of NoC and Their Application to Memory-Centric NoC

Donghyun Kim, Kwanho Kim, Joo-Young Kim, Seung-Jin Lee, Hoi-Jun Yoo
2007 First International Symposium on Networks-on-Chip (NOCS'07)  
As for architecture level solutions, topology selection, chip-aware protocol design, and On-Chip Serialization (OCS) for link area reduction are explained.  ...  This paper describes real chip implementation issues of Network-on-Chip (NoC) and their solutions along with series of chip design examples.  ...  As a result, the aligned packet format provides helps for efficient hardware implementation for NoCs. C. On-chip Serialization On-chip serialization (OCS) technique reduces the link width.  ... 
doi:10.1109/nocs.2007.40 dblp:conf/nocs/KimKKLY07 fatcat:snqnw4jow5dktgdmo5gmg7lpau

Networks-on-chip and Networks-in-Package for High-Performance SoC Platforms

Kangmin Lee, Se-joong Lee, Donghyun Kim, Kwanho Kim, Gawon Kim, Joungho Kim, Hoi-jun Yoo
2005 2005 IEEE Asian Solid-State Circuits Conference  
A structured packet-switched Networks-on-Chip (NoC) is designed and implemented for high-performance heterogeneous SoC design platform. The chip integrates  ...  The NoC architecture uses layered protocols and packet-switched networks which consist of on-chip routers, links, and network interfaces on a predefined topology, as depicted in Fig. 1 .  ...  As a result, 22% power saving is obtained on 8x8 crossbar. 3) Low-Energy Coding on On-chip Serial Link [4] On-chip source-synchronous serial communication has many advantages over multi-bit parallel  ... 
doi:10.1109/asscc.2005.251783 fatcat:4ql6pmz2orhcfdcnufm2dcsarq

CDMA Technique with Inter-process Communication

V. Ravichandran, G.K.D. Prasanna Venkatesan
2014 Research Journal of Applied Sciences Engineering and Technology  
The data transfers over IP-Core based interconnect is implemented on gate level. The latency and throughput values are obtained for variable payload size.  ...  transmission and receiving circuits, along with ip-cores and reduces the processing time and resource utilization.  ...  Lahiri et al. (2005) presented design of communication architectures for high-performance and energy-efficient systems-on-chip.  ... 
doi:10.19026/rjaset.7.450 fatcat:kcinbmfplja2narsij5t6uapyu

An Interconnection Architecture for Seamless Inter and Intra-Chip Communication Using Wireless Links

Md Shahriar Shamim, Jagan Muralidharan, Amlan Ganguly
2015 Proceedings of the 9th International Symposium on Networks-on-Chip - NOCS '15  
Several on-chip network architectures are proposed to improve the design flexibility and communication efficiency of such multicore chips.  ...  rather than a communication architecture for a system as a whole.  ...  As conventional metallic interconnects become the bottleneck of Network-on-Chips, wireless NoC architectures are proposed [9] , which significantly improves the energy efficiency and bandwidth of on-chip  ... 
doi:10.1145/2786572.2786581 dblp:conf/nocs/ShamimMG15 fatcat:vmf5r324ejamvc5yopfobcfquq

Design of an Interconnect Architecture and Signaling Technology for Parallelism in Communication

Jongsun Kim, I. Verbauwhede, M.-C.F. Chang
2007 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
The need for efficient interconnect architectures beyond the conventional time-division multiplexing (TDM) protocol-based interconnects has been brought on by the continued increase of required communication  ...  technology that exploits parallelism in board-level communication, resulting in shorter latency and higher concurrency on a shared bus or link: the proposed source synchronous CDMA interconnect (SS- CDMA-I  ...  ACKNOWLEDGMENT The authors would like to thank Samsung, Gyunggi-Do, South Korea, for fabricating the chip.  ... 
doi:10.1109/tvlsi.2007.900739 fatcat:dogc5re4hjdm7pjmtaouhpfnuq

NETWORK ON-CHIP AND ITS RESEARCH CHALLENGES

Paramasivam K.
2015 ICTACT Journal on Microelectronics  
Networks-On-Chip (NoCs) have been proposed as a promising solution for power, performance demands and scalability of next generation Systems-On-Chip (SOCs) to overcome the several challenges of current  ...  In this article, NoC, its architecture and features are presented. Further the article is extended with research challenges.  ...  Network on Chip is a very active research field with many practical applications in industry. This work focuses on the system, network and link level issues of the communication infrastructure.  ... 
doi:10.21917/ijme.2015.0015 fatcat:butio7bjjjbgxdtrqnquaei2wa

Low-power network-on-chip for high-performance SoC design

Kangmin Lee, Se-Joong Lee, Hoi-Jun Yoo
2006 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
An energy-efficient network-on-chip (NoC) is presented for possible application to high-performance system-onchip (SoC) design.  ...  Various low-power techniques such as low-swing signaling, partially activated crossbar, serial link coding, and clock frequency scaling are devised, and applied to achieve the power-efficient on-chip communications  ...  The NoC architecture uses layered protocols and packet-switched networks which consist of on-chip routers, links, and network interfaces on a predefined topology, as illustrated in Fig. 1 .  ... 
doi:10.1109/tvlsi.2005.863753 fatcat:bkrguqc3tvfzrfz4355asucr7y

High-Throughput Partially Parallel Inter-Chip Link Architecture for Asynchronous Multi-Chip NoCs

Naoya ONIZAWA, Akira MOCHIZUKI, Hirokatsu SHIRAHAMA, Masashi IMAI, Tomohiro YONEDA, Takahiro HANYU
2014 IEICE transactions on information and systems  
a partially parallel inter-chip link architecture for asynchronous multi-chip Network-on-Chips (NoCs).  ...  The proposed asynchronous link based on level-encoded dual-rail (LEDR) encoding transmits several bits in parallel that are received by detecting the phase information of the LEDR signals at each serial  ...  Conclusion A high-throughput partially parallel inter-chip link architecture has been proposed for asynchronous multi-chip NoCs.  ... 
doi:10.1587/transinf.e97.d.1546 fatcat:xkde57mxwzfyxlrja2jggpm6iu

Link Division Multiplexing (LDM) for Network-on-Chip Links

Arkadiy Morgenshtein, Avinoam Kolodny, Ran Ginosar
2006 2006 IEEE 24th Convention of Electrical & Electronics Engineers in Israel  
Large Systems-on-Chip (SoC) can employ packet-switched Networks on-Chip with Quality-of-Service (QNoC) architecture. Communication in QNoC links typically involves Time Division Multiplexing (TDM).  ...  In this paper we propose the Link Division Multiplexing (LDM) technique based on optimal division of link wires among the data blocks of various applications and QoS levels that are transmitted through  ...  SUMMARY Link Division Multiplexing (LDM) technique was proposed in this paper. LDM is applied to packetswitched Networks on-Chip with Quality-of-Service (QNoC) architecture.  ... 
doi:10.1109/eeei.2006.321064 fatcat:yusriny2lnfa5mkov7gdosdiqi

KiloCore: A Fine-Grained 1,000-Processor Array for Task-Parallel Applications

Brent Bohnenstiehl, Aaron Stillmaker, Jon Pimentel, Timothy Andreas, Bin Liu, Anh Tran, Emmanuel Adeagbo, Bevan Baas
2017 IEEE Micro  
known benefits in performance and efficiency, with many modern chip designs focusing on integrating increasing numbers of processors on a single die instead of increasing the complexity of a smaller number  ...  high energy efficiency alongside high performance. 6 Semiconductor fabrication technologies continue to provide increasing levels of integration, 7 offering opportunities for new architecture designs.  ...  KiloCore uses complementary circuit and packet networks to efficiently support these links.  ... 
doi:10.1109/mm.2017.34 fatcat:oj5tyfgzmvdyzougnpaz4egrye
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