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CMSM: An efficient and effective Code Management for Software Managed Multicores

Ke Bai, Jing Lu, Aviral Shrivastava, Bryce Holton
2013 2013 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)  
Managed multicores) that results in efficient code management execution on the local scratchpad memory.  ...  As we scale the number of cores in a multicore processor, scaling the memory hierarchy is a major challenge. Software Managed Multicore (SMM) architectures are one of the promising solutions.  ...  The first step in code management is to assign some space in the local scratchpad memory for managing code.  ... 
doi:10.1109/codes-isss.2013.6658998 dblp:conf/codes/BaiLSH13 fatcat:vllxmhwxabdhpm7mhpkpcmn22e

Dynamic heterogeneity and the need for multicore virtualization

Philip M. Wells, Koushik Chakraborty, Gurindar S. Sohi
2009 ACM SIGOPS Operating Systems Review  
As the computing industry enters the multicore era, exponential growth in the number of transistors on a chip continues to present challenges and opportunities for computer architects and system designers  ...  We show that multicore virtualization operates with minimal overhead, and that it enables several novel resource management applications for improving both performance and reliability.  ...  We argue that efficiently managing the use of all on-chip cores will soon become equally as challenging for software as extracting concurrency.  ... 
doi:10.1145/1531793.1531797 fatcat:mgrtesoh7zawjf7potq6nc2wmq

SWARM: A Parallel Programming Framework for Multicore Processors

David A. Bader, Varun Kanade, Kamesh Madduri
2007 2007 IEEE International Parallel and Distributed Processing Symposium  
We introduce SWARM (SoftWare and Algorithms for Running on Multi-core), a portable open-source parallel library of basic primitives that fully exploit multicore processors.  ...  Continued performance on multicore processors now requires the exploitation of concurrency at the algorithmic level.  ...  on one thread * / on_one_thread { .... .... } Memory management.  ... 
doi:10.1109/ipdps.2007.370681 dblp:conf/ipps/BaderKM07 fatcat:oqtbqmbzuzbrfihus5b4e47qgu

A Design of Pipelined Architecture for on-the-Fly Processing of Big Data Streams

Usamah Algemili, Simon Berkovich
2015 International Journal of Advanced Computer Science and Applications  
The system overpasses internal memory constrains of multicore architectures by applying forced interrupts and crossbar switching.  ...  Parallel computing relies on parallel programs that may encounter internal memory constrains. In addition, parallel computing needs special skillset of programming as well as software conversions.  ...  Forth, Local memory access that is simple and regular, and it should avoid pointer tracking code.  ... 
doi:10.14569/ijacsa.2015.060104 fatcat:rffyrbnqvvg5fczycrhze2i664

Implementing OpenMP on a high performance embedded multicore MPSoC

Barbara Chapman, Lei Huang, Eric Biscondi, Eric Stotzer, Ashish Shrivastava, Alan Gatherer
2009 2009 IEEE International Symposium on Parallel & Distributed Processing  
It must also be capable of supporting the mapping of different software tasks, or components, to the devices configured in a given architecture.  ...  In this paper we discuss our initial experiences adapting OpenMP to enable it to serve as a programming model for high performance embedded systems.  ...  Software for embedded systems will become more complex, as multicore hardware will enable more functions to be implemented on the same device.  ... 
doi:10.1109/ipdps.2009.5161107 dblp:conf/ipps/ChapmanHBSSG09 fatcat:prqzkfif4fhc7m2di7gbnejqeq

Toward Efficient Execution of RVC-CAL Dataflow Programs on Multicore Platforms

Ilkka Hautala, Jani Boutellier, Teemu Nyländen, Olli Silvén
2018 Journal of Signal Processing Systems  
In this work, a runtime for executing Dataflow Process Networks (DPN) on multicore platforms is proposed.  ...  The proposed runtime is benchmarked on desktop and server multicore platforms using five different applications from video coding and telecommunication domains.  ...  For this reason programmers have to invest a lot of effort in efficient mapping of their software on these multicore architectures.  ... 
doi:10.1007/s11265-018-1339-x fatcat:txjhz22e3vgb3cphnql32wki7y

High-Performance Energy-Efficient Multicore Embedded Computing

A. Munir, S. Ranka, A. Gordon-Ross
2012 IEEE Transactions on Parallel and Distributed Systems  
The increase in on-chip transistor density exacerbates power/thermal issues in embedded systems, which necessitates novel hardware/software power/thermal management techniques to meet the ever-increasing  ...  With Moore's law supplying billions of transistors on-chip, embedded systems are undergoing a transition from single-core to multicore to exploit this high-transistor density for high performance.  ...  Both CMPs and MPSoCs rely on HPEEC hardware/software techniques for delivering high performance per watt and meeting diverse application requirements.  ... 
doi:10.1109/tpds.2011.214 fatcat:vagqmojdsjevvc2u2ewqrcjjpq

Hybrid Programming Model for Implicit PDE Simulations on Multicore Architectures [chapter]

Dinesh Kaushik, David Keyes, Satish Balay, Barry Smith
2011 Lecture Notes in Computer Science  
Even though OpenMP based parallelism is easier to implement (with in a subdomain assigned to one MPI process for simplicity), getting good performance needs attention to data partitioning issues similar  ...  At the implementation level, the effects of cache locality, update management, work division, and synchronization frequency are studied.  ...  Acknowledgments We thank William Gropp of University of Illinois at Urbana Champaign for many helpful discussions.  ... 
doi:10.1007/978-3-642-21487-5_2 fatcat:cqnxrmg235h2hjphs2x3eey3je

Flextream: Adaptive Compilation of Streaming Applications for Heterogeneous Architectures

Amir H. Hormati, Yoonseo Choi, Manjunath Kudlur, Rodric Rabbah, Trevor Mudge, Scott Mahlke
2009 2009 18th International Conference on Parallel Architectures and Compilation Techniques  
Increasing demand for performance and efficiency has driven the computer industry toward multicore systems.  ...  of cores, available memory or bandwidth).  ...  Acknowledgement Much gratitude goes to the anonymous referees who provided excellent feedback on this work.  ... 
doi:10.1109/pact.2009.39 dblp:conf/IEEEpact/HormatiCKRMM09 fatcat:e3etmhtkkbgk5flpj5bqvvbthu

Parallelizing Complex Streaming Applications on Distributed Scratchpad Memory Multicore Architecture

Shin-Kai Chen, Cheng-Yu Hung, Ching-Chih Chen, Chih-Wei Liu
2013 International journal of parallel programming  
In this study, we developed an efficient design flow for parallelizing multimedia applications on a distributed scratchpad memory multicore architecture.  ...  For less hardware complexity and power consumption, the distributed scratchpad memory architecture is considered, instead of the cache memory architecture.  ...  Memory allocation techniques, such as dynamic code mapping and circular stack management, allow us to assign a large data segment to a single core; however, this technique could create overhead associated  ... 
doi:10.1007/s10766-013-0256-7 fatcat:f5gwz3str5a2jlnjyhqfshf4my

Stream Compilation for Real-Time Embedded Multicore Systems

Yoonseo Choi, Yuan Lin, Nathan Chong, Scott Mahlke, Trevor Mudge
2009 2009 International Symposium on Code Generation and Optimization  
However, many of the advantages of switching to multicore hinge on the assumption that software development is simpler and less costly than hardware development.  ...  Specifically, real-time deadlines and memory size limitations are not handled by conventional stream partitioning and scheduling techniques.  ...  Each SPE is equipped with a software-managed local memory and a DMA engine, and mainly specialized for heavy-duty data processing.  ... 
doi:10.1109/cgo.2009.27 dblp:conf/cgo/ChoiLCMM09 fatcat:ws7yxc5p4re67dqllg3uox32se

An Integrated Framework for Dependable and Revivable Architectures Using Multicore Processors

Weidong Shi, Hsien-Hsin S. Lee, Laura `Falk, Mrinmoy Ghosh
2006 SIGARCH Computer Architecture News  
To provide efficient service recovery and thus improve service availability, we propose a novel delta state backup and recovery on-demand mechanism in INDRA that substantially outperforms conventional  ...  This paper presents a high-availability system architecture called INDRA -an INtegrated framework for Dependable and Revivable Architecture that enhances a multicore processor (or CMP) with novel security  ...  For each virtual memory page, there is a Local memory checkpoint TimeStamp (LTS).  ... 
doi:10.1145/1150019.1136520 fatcat:2cgtp3yiincg3j3o3lyjazv7t4

From Scilab to multicore embedded systems: Algorithms and methodologies

George Goulas, Panayiotis Alefragis, Nikolaos S. Voros, Christos Valouxis, Christos Gogos, Nikolaos Kavvadias, Grigoris Dimitroulakos, Kostas Masselos, Diana Goehringer, Steven Derrien, Daniel Menard, Olivier Sentieys (+8 others)
2012 2012 International Conference on Embedded Computer Systems (SAMOS)  
This paper presents the methodology and algorithms for the creation of parallel software written in Scilab source code for multicore embedded processors in the context of the "Architecture oriented paraLlelization  ...  The ALMA parallelization approach in a nutshell attempts to manage the complexity of the task by alternating focus between very localized and holistic view program optimization strategies.  ...  On one hand there is a definite need for efficient tools for experts in parallel programming, on the other hand there is an increasing demand for tools to enable non-experts to produce efficient parallel  ... 
doi:10.1109/samos.2012.6404184 dblp:conf/samos/GoulasAVVGKDMGDMSHSOBRSKM12 fatcat:ldkdwbhc5batjfkzi6vphfvxbq

Hybrid MPI/openMP application on multicore architectures: the case of profit-sharing life insurance policies valuation

P. L. De Angelis, F. Perla, P. Zanetti
2013 Applied Mathematical Sciences  
The DISAR (Dynamic Investment Strategy with Accounting Rules) system -an Asset-Liability Management software for monitoring portfolios of life insurance policies -has been proven to be extremely efficient  ...  We discuss our experiences on two different multicore architectures -an UMA machine and a NUMA one -and we present a set of techniques and software tools that we implement to face the associated problems  ...  In this work we want to investigate the performance of Asset-Liability Management (ALM) software for monitoring portfolios of life insurance policies on multicore architectures.  ... 
doi:10.12988/ams.2013.37357 fatcat:66n26qiyyne4th2mtgu43ofq4a

The impact of diverse memory architectures on multicore consumer software

George Russel, Colin Riley, Neil Henning, Uwe Dolinsky, Andrew Richards, Alastair F. Donaldson, Alexander S. van Amesfoort
2011 Proceedings of the 2011 ACM SIGPLAN Workshop on Memory Systems Performance and Correctness - MSPC '11  
Memory architectures need to adapt in order for performance and scalability to be achieved in software for multicore systems.  ...  In this paper, we discuss the impact of techniques for scalable memory architectures, especially the use of multiple, non-cache-coherent memory spaces, on the implementation and performance of consumer  ...  Elaborations on this technique could implement alternative behaviours, such as on-demand code loading for functions not present in local memory.  ... 
doi:10.1145/1988915.1988925 dblp:conf/pldi/RussellRHDRDA11 fatcat:2ufoqq3jwvehnlwwbn5azpbe4m
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