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Small FPGA Based Multiplication-Inversion Unit for Normal Basis Representation in GF(2m)

Jeremy Metairie, Arnaud Tisserand, Emmanuel Casseau
2015 2015 IEEE Computer Society Annual Symposium on VLSI  
Our solution is based on permuted normal basis, Massey-Omura multiplication and Itoh-Tsujii inversion algorithms. Our FPGA implementations show better efficiency for large fields.  ...  We propose a new combined multiplication-inversion unit for binary field extensions and halving based ECC methods optimized for FPGAs.  ...  We use Gaussian normal basis (GNB, a specific type of normal basis) due to its very low hardware complexity for the implementation of multiplication by M 0 [12] .  ... 
doi:10.1109/isvlsi.2015.32 dblp:conf/isvlsi/MetairieTC15 fatcat:smm2hzee75gwboz3lh7w6jhdem

FPGA High Performance Pipelined Architecture Of Elliptic Scalar Multiplication Over GF(2m) for IOT

Kiran Sulthana S
2017 International Journal for Research in Applied Science and Engineering Technology  
In our hybrid multiplier, the simple algorithm performs the initial recursion whereas the general algorithm performs the final multiplication of small sizes.  ...  The efficiency is largely affected by the underlying arithmetic primitives. Multiplication and Inversion are the two most important primitive fields which FPGA design of our concept reveals.  ...  Their design adapted a digit-serial approach in GF multiplication and GF division in order to construct an efficient elliptic curve multiplier using projective coordinates.  ... 
doi:10.22214/ijraset.2017.4058 fatcat:6p3jp245cfhthbhl7r7rhi56ay

A Vendor-Neutral Unified Core for Cryptographic Operations in GF(p) and GF(2m) Based on Montgomery Arithmetic

Martin Schramm, Reiner Dojen, Michael Heigl
2018 Security and Communication Networks  
In the context of a limited amount of resources that typical IoT devices will exhibit, due to energy efficiency requirements, efficient hardware structures in terms of time, area, and power consumption  ...  In the emerging IoT ecosystem in which the internetworking will reach a totally new dimension the crucial role of efficient security solutions for embedded devices will be without controversy.  ...  Conflicts of Interest The authors declare that there are no conflicts of interest regarding the publication of this paper.  ... 
doi:10.1155/2018/4983404 fatcat:pzcx23iplrdr7bh2uhe26zpane

Low complexity word-level sequential normal basis multipliers

A. Reyhani-Masoleh, M.A. Hasan
2005 IEEE transactions on computers  
For efficient hardware implementation of finite field arithmetic units, the use of a normal basis is advantageous.  ...  In this paper, two classes of architectures for multipliers over the finite field GF ð2 m Þ are proposed.  ...  ACKNOWLEDGMENTS This work has been supported in part by an NSERC postdoctoral fellowship awarded to A. Reyhani-Masoleh and in part by an NSERC grant awarded to M.A. Hasan.  ... 
doi:10.1109/tc.2005.29 fatcat:ifpyhhpubva2fcsvi2j4i22l2y

Design of Fast Finite Field Multiplier based on Noramal Basis

Jae Yeon Choi
2015 Indian Journal of Science and Technology  
Additional cost is not required to squaring operation; the finite field algebraic calculation using normal basis field arithmetic has advantages.  ...  Using this property, more simplified schematic of multiplier which needs a half of latency than the other existing multipliers is proposed and designed.  ...  C N is greater than or equal to 2m-1. If C N = 2m-1, then the normal basis is known as an optimal normal basis.  ... 
doi:10.17485/ijst/2015/v8i34/86663 fatcat:4rrrl6wosnafheadr6xmntlgdy

Efficient digit-serial normal basis multipliers over binary extension fields

Arash Reyhani-Masoleh, M. Anwar Hasan
2004 ACM Transactions on Embedded Computing Systems  
We also consider two special cases of optimal normal bases for the two digit-serial architectures. A straightforward implementation leaves gate redundancy in both of them.  ...  In this article, two digit-serial architectures for normal basis multipliers over GF(2 m ) are presented. These two structures have the same gate count and gate delay.  ...  ACKNOWLEDGMENTS This work has been supported in part by an NSERC postdoctoral fellowship awarded to A. Reyhani-Masoleh and in part by an NSERC grant awarded to M. A. Hasan.  ... 
doi:10.1145/1015047.1015053 fatcat:7tkcroydxbh5dbousx6gjwjwbe

Implementation And Analysis Of Elliptic Curve Cryptosystems Over Polynomial Basis And Onb

Yong-Je Choi, Moo-Seop Kim, Hang-Rok Lee, Ho-Won Kim
2007 Zenodo  
In general, it is said that normal bases, especially optimal normal bases (ONB) which are special cases on normal bases, are efficient for the implementation in hardware in comparison with polynomial bases  ...  And, in addition, we predicted the efficiency of two elliptic curve cryptosystems using these field arithmetic operators.  ...  Any bases in both can be used for ECCs, however, some special cases such as trinomial bases, pentanomial bases and optimal normal bases (ONBs) are, in practice, used for the purpose of efficient operations  ... 
doi:10.5281/zenodo.1330374 fatcat:ypet7u6pqbfofesgswghjbbj6m

Efficient algorithms and architectures for field multiplication using Gaussian normal bases

A. Reyhani-Masoleh
2006 IEEE transactions on computers  
Recently, implementations of normal basis multiplication over the extended binary field GF ð2 m Þ have received considerable attention.  ...  A class of low complexity normal bases called Gaussian normal bases has been included in a number of standards, such as IEEE [1] and NIST [2] for an elliptic curve digital signature algorithm.  ...  Moreover, for type II optimal normal bases, they also match the ones of the multipliers proposed in [12] and [33] .  ... 
doi:10.1109/tc.2006.10 fatcat:lllysbpbmbhpvi7jx6hqlsfmmi

Elliptic Curve Scalar Multiplier Design Using FPGAs [chapter]

Lijun Gao, Sarvesh Shrivastava, Gerald E. Sobelman
1999 Lecture Notes in Computer Science  
This implementation utilizes the internal SRAM/registers of the FPGA and has the whole scalar multiplier implemented within a single FPGA chip.  ...  One example of the VHDL simulation results is shown in Fig. 9 for m = 39 and type II optimal normal basis [14] .  ...  Previous work in this area is based on a coprocessor for arithmetic operations over GF (2 155 ) using a gate array [11] .  ... 
doi:10.1007/3-540-48059-5_22 fatcat:pfpgb3qtzfbrndgqmjinwaexmm

Fault Detection Multipliers in Polynomial and Normal Basis

Siddharth Shelly, Babu T Chacko
2010 International Journal of Computer Applications  
New architectures are developed to detect erroneous outputs caused by certain types of faults in bit-serial polynomial basis multipliers and digit-serial normal basis multipliers over finite fields of  ...  In many cryptographic schemes, the most time consuming basic arithmetic operation is the finite field multiplication and its hardware implementation for bit parallel operation may require millions of logic  ...  Ie if the value of t=1 it becomes optimal normal basis of type I and if the value of t=2 it becomes optimal normal basis of type II. So the parity is different for both the type.  ... 
doi:10.5120/114-229 fatcat:t5vuxq2qanfq5gi4j2yrsad4yi

Elliptic Curve Cryptoprocessor Implementation on a Nano FPGA: Interesting for Resource-Constrained Devices

Hilal Houssain, Turki F. Al-Somani
2012 International Journal of RFID Security and Cryptography  
The synthesis results show that the targeted Nano FPGA can't exceed the values of m ≤ 11 bits.  ...  Nano FPGAs offer groundbreaking possibilities in power, size, lead-times, operating temperature and cost. To the best of our knowledge, this is the first ECC implementation on Nano FPGAs.  ...  The authors would like to acknowledge the support of Umm Al-Qura University, Makkah, Saudi Arabia and the support of LIMOS, CNRS, University Blaise Pascal, Clermont-Ferrand II, France.  ... 
doi:10.20533/ijrfidsc.2046.3715.2012.0006 fatcat:fvfezzjofng6tmpsp326g6abtm

New Architectures for Digit-Level Single, Hybrid-Double, Hybrid-Triple Field Multiplications and Exponentiation Using Gaussian Normal Bases

Hayssam El-Razouk, Arash Reyhani-Masoleh
2016 IEEE transactions on computers  
Gaussian normal bases (GNBs) are special set of normal bases (NBs) which yield low complexity GF (2 m ) arithmetic operations.  ...  In this paper, we present new architectures for the digit-level single, hybrid-double, and hybrid-triple multiplication of GF (2 m ) elements based on the GNB representation for odd values of m > 1.  ...  In particular, Gaussian normal bases (GNBs) -a special subset of the NBs which offer field operations with smaller area and time overheads compared to the general NB -are often used for efficient hardware  ... 
doi:10.1109/tc.2015.2481408 fatcat:37s5j6rxezgwtggolstffkqk3q

Concurrent Error Detection in Multiplexer-Based Multipliers for Normal Basis of GF(2 m ) Using Double Parity Prediction Scheme

Chiou-Yng Lee, Che Wun Chiou, Jim-Min Lin
2009 Journal of Signal Processing Systems  
To obtain reliable cryptographic applications, a novel concurrent error detection (CED) architecture to detect erroneous outputs in multiplexer-based normal basis (NB) multiplier over GF (2 m ) using the  ...  It is also frequently used in performing point operations in elliptic curve groups.  ...  Various efficient bit-parallel and bit-serial architectures for normal basis multiplication over GF(2 m ) have been developed in [11] [12] [13] 23] .  ... 
doi:10.1007/s11265-009-0361-4 fatcat:r5ek7txpgfab3b4ymcosxcikxq

Hardware architectures for public key cryptography

Lejla Batina, Sıddıka Berna Örs, Bart Preneel, Joos Vandewalle
2003 Integration  
The basic operation for ECC is point multiplication which relies on efficient finite field multiplication. Commonly used finite fields in ECC protocols are GF (p) and GF (2 n ).  ...  The basic operation for RSA is multiplication in GF (p). As a consequence, a substantial amount of research is focused on efficient and secure implementation of modular multiplication in hardware.  ...  . • Type III composite field: A subfield GF (2 n )-Type II optimal normal basis and an extension field GF (2 nm )-Type II optimal normal basis.  ... 
doi:10.1016/s0167-9260(02)00053-6 fatcat:u5pkdeitprh77hcaaui66nzv24

Bit-Serial and Bit-Parallel Montgomery Multiplication and Squaring over GF(2^m)

Arash Hariri, Arash Reyhani-Masoleh
2009 IEEE transactions on computers  
In this paper, we consider the Montgomery multiplication in the binary extension fields and study different structures of bit-serial and bit-parallel multipliers.  ...  Then, we consider type-II irreducible pentanomials and design two bit-parallel multipliers which are comparable to the best finite field multipliers reported in the literature.  ...  This work has been supported in part by an NSERC Discovery grant awarded to Arash Reyhani-Masoleh.  ... 
doi:10.1109/tc.2009.70 fatcat:huco55p7tfcttmadd6rpckfq5y
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