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A Dynamic Programming Approach to Energy-Efficient Scheduling on Multi-FPGA based Partial Runtime Reconfigurable Systems

Chao Jing, Qi Song
2017 TELKOMNIKA (Telecommunication Computing Electronics and Control)  
To tackle these challenges, based on the theory of dynamic programming, we have designed and implemented an energy-efficient scheduling on multi-FPGA systems.  ...  This paper has been studied an important issue of energy-efficient scheduling on multi-FPGA systems.  ...  In Section IV, we detail the dynamic programming based energy-efficient algorithm on multi-FPGA based reconfigurable systems.  ... 
doi:10.12928/telkomnika.v15i1.3878 fatcat:th2r2xzsqvgulelvybjnbxzggm

Lattice-Based Scheduling for Multi-FPGA Systems

Teng Yu, Bo Feng, Mark Stillwell, Liucheng Guo, Yuchun Ma, John Thomson
2018 2018 International Conference on Field-Programmable Technology (FPT)  
FPGAs have been shown to be fast and power efficient for particular tasks, yet scheduling on FPGA-based multi-accelerator systems is challenging when workloads vary significantly in granularity in terms  ...  We present a novel approach for dynamically scheduling tasks on networked multi-FPGA systems which maintains high performance, even in the presence of irregular tasks.  ...  We present a novel dynamic scheduling approach for multi-FPGA systems, based on a partial order representation of tasks and a ranking methodology.  ... 
doi:10.1109/fpt.2018.00063 dblp:conf/fpt/YuFSGMT18 fatcat:zqzktchmlncx3fmhsswhjowgku

Facilitating Easier Access to FPGAs in the Heterogeneous Cloud Ecosystems

Umar Ibrahim Minhas, Roger Woods, Georgios Karakonstantis
2019 Zenodo  
With FPGAs being increasingly integrated into existing software-based heterogeneous cloud environments, novel evaluation mechanisms are required to reveal the energyperformance trade-offs of accelerators  ...  For FPGAs, this also requires reconsideration of scheduling policies and reconfiguration methods with an aim to integrate software-based approaches as well as optimizations for broader workload sizes.  ...  The second challenge investigates reconfiguration overhead on FPGAs [3] incurred due to multi-task execution in cloud systems.  ... 
doi:10.5281/zenodo.2586984 fatcat:j5g4ajku3rcmhmeujzzuafou4a

A Hardware and Software Task-scheduling Framework Based on CPU+FPGA Heterogeneous Architecture in Edge Computing

Zongwei Zhu, Junneng Zhang, Jinjin Zhao, Jing Cao, Duan Zhaoa, Gangyong Jia, Qingyong Meng
2019 IEEE Access  
INDEX TERMS FPGA, edge computing, task scheduling, heterogeneous system, dynamic partial reconfigurable system.  ...  Nontheless, the performance depends also on the scheduling efficiency between software tasks on CPUs and hardware tasks on FPGAs.  ...  .: Hardware and Software Task-Scheduling Framework Based on CPU+FPGA Heterogeneous Architecture be completed at t 9 .  ... 
doi:10.1109/access.2019.2943179 fatcat:lnhvirym7bgsxp336h3rvolysi

A Case Study: Task Scheduling Methodologies for High Speed Computing Systems

Mahendra Vucha, Arvind Rajawat
2014 International Journal of Embedded Systems and Applications  
The efficient task scheduling is critical to obtain optimized performance in heterogeneous computing Systems (HCS).  ...  The comparative study of scheduling methodologies for high speed computing systems has been carried out based on the attributes of platform & application as well.  ...  Online scheduling of Software Tasks (ST), Hardware Tasks (HT) and Hybrid Tasks (HST) proposed [6] for CPU-FPGA platform, where ST executes only on CPU, HT executes only on FPGA and the HST execute on  ... 
doi:10.5121/ijesa.2014.4401 fatcat:dtjqbhh7zbdbjoqddi5cd5o6v4

Facilitating Easier Access to FPGAs in the Heterogeneous Cloud Ecosystems

Umar Minhas, Roger Woods, Georgios Karakonstantis
2018 2018 28th International Conference on Field Programmable Logic and Applications (FPL)  
With FPGAs being increasingly integrated into existing software-based heterogeneous cloud environments, novel evaluation mechanisms are required to reveal the energyperformance trade-offs of accelerators  ...  (FPGAs, GPUs, etc) using high-level heterogeneous programming environments.  ...  The second challenge investigates reconfiguration overhead on FPGAs [3] incurred due to multi-task execution in cloud systems.  ... 
doi:10.1109/fpl.2018.00083 dblp:conf/fpl/MinhasWK18 fatcat:z2hsqubwavax7ftepbqvurks7m

A Run-Time Dynamic Reconfigurable Computing System for Lithium-Ion Battery Prognosis

Shaojun Wang, Datong Liu, Jianbao Zhou, Bin Zhang, Yu Peng
2016 Energies  
Our research focuses on the lithium-ion battery RUL estimation with a RVM algorithm implemented on a novel FPGA-based dynamic reconfigurable computing architecture.  ...  on embedded systems brings a significant challenge and this requires efficient embedded computing system being developed.  ...  The partition of computing tasks is realized by a multi-objective optimization based on dynamic reconfigurable RVM.  ... 
doi:10.3390/en9080572 fatcat:mbnenpyknrg3fa4f4vhjyn5obm

On the design, control, and use of a reconfigurable heterogeneous multi-core system-on-a-chip

Tyrone Tai-On Kwok, Yu-Kwong Kwok
2008 Proceedings, International Parallel and Distributed Processing Symposium (IPDPS)  
Experimental evaluation demonstrates significant system efficiency of the proposed heterogeneous multi-core system in terms of computation and power consumption.  ...  We have built a prototype of the system using FPGAs.  ...  In this paper, we illustrate this concept by describing the design, control, and use of our proposed dynamically reconfigurable heterogeneous multi-core system based on Field Programmable Gate Arrays (  ... 
doi:10.1109/ipdps.2008.4536165 dblp:conf/ipps/KwokK08 fatcat:gvjeimrq4rhghlzcqijolmrycy

Enabling Efficient and Flexible FPGA Virtualization for Deep Learning in the Cloud [article]

Shulin Zeng, Guohao Dai, Hanbo Sun, Kai Zhong, Guangjun Ge, Kaiyuan Guo, Yu Wang, Huazhong Yang
2020 arXiv   pre-print
On the other hand, to overcome the heavy re-compilation overheads, we propose a tiling-based instruction frame package design and two-stage static-dynamic compilation.  ...  To solve these problems, we introduce a novel virtualization framework for instruction architecture set (ISA) based on DNN accelerators by sharing a single FPGA.  ...  Evaluation on Multi-Task Throughput.  ... 
arXiv:2003.12101v1 fatcat:zzwoc4hp5rgpbehz2wr6d2mwiq

Evaluation of Static Mapping for Dynamic Space-Shared Multi-task Processing on FPGAs

Umar Ibrahim Minhas, Roger Woods, Georgios Karakonstantis
2021 Journal of Signal Processing Systems  
efficient mapping of heterogeneous tasks onto the FPGA.  ...  AbstractWhilst FPGAs have been used in cloud ecosystems, it is still extremely challenging to achieve high compute density when mapping heterogeneous multi-tasks on shared resources at runtime.  ...  Optimization of the system's resource utilization in time and space when executing these tasks in an area-shared manner on FPGAs, can lead to suboptimal compute density and system throughput.  ... 
doi:10.1007/s11265-020-01633-z fatcat:o6b3y6ejynfupci53mj6dqrye4

On-Chip Hardware Accelerator For DSP Applications

2019 International journal of recent technology and engineering  
The proposed multi core platform has been realized on FPGA and few DSP applications are executed on the processing elements of the platform to validate its performance.  ...  This article presents new hardware accelerating platform comprised of heterogeneous multi core processing elements integrated on single chip FPGA.  ...  The researchers in [16] [17] designed multi core high speed computing system on FPGA device to enhance the execution speed of the applications.  ... 
doi:10.35940/ijrte.c6079.098319 fatcat:gtssfhzxurfv7bbg7sovvp67si

Dynamic scheduling Monte-Carlo framework for multi-accelerator heterogeneous clusters

Anson H.T. Tse, David B. Thomas, K.H. Tsoi, Wayne Luk
2010 2010 International Conference on Field-Programmable Technology  
This framework enables different hardware accelerators in a multi-accelerator heterogeneous cluster to work collaboratively on a single application.  ...  A cluster with 8 Virtex-5 xc5vlx330t FPGAs and 8 Tesla C1060 GPUs using the proposed framework provides 44 times speedup and 19.6 times improved energy efficiency over a cluster with 16 AMD Phenom 9650  ...  A dynamic scheduling policy based on the EAL could also be developed such that it allocates the tasks to the accelerators based on a certain energy budget or time budget which can vary during run time.  ... 
doi:10.1109/fpt.2010.5681495 dblp:conf/fpt/TseTTL10 fatcat:x6e7st6p4bbh3jcuf54atwcwse

Operating System Design Challenges for a Reconfigurable Computing Environment

B. Abirami, K. Sridhar, V. Vaidhyanathan
2015 Indian Journal of Science and Technology  
The advantages of using the Field Programmable Gate Array (FPGA) in Reconfigurable Computing System (RCS) to handle complex applications and to increase the efficiency and throughput of the system are  ...  The different challenges faced by an Operatin System in handling the applications executed by a conventional CPU are analysed.  ...  Support for multi tasking. Earlier work on operating systems for reconfigurable computing is available in literature.  ... 
doi:10.17485/ijst/2015/v8i35/86696 fatcat:5wfxyrvotjeffgq2hdqdi2lnvy

Design and Program Multi-processor Platform for High-performance Embedded Processing

Yijun Liu, Zhenkun Li
2009 Journal of Software  
Multi-CPU/FPGA Platform Based Heterogeneous Mul- tiprocessor Prototyping: New Challenges for Embedded Software Designers The 19th IEEE/IFIP International Symposium on Rapid System Prototyping  ...  Moreover, efficiency of some important program ‘kernels’. In one tasks are loaded dynamically.  ... 
doi:10.4304/jsw.4.10.1069-1075 fatcat:nn372jjpjjaqvffyhmztwyv6hu

A Novel Methodology for Task Distribution in Heterogeneous Reconfigurable Computing System

Mahendra Vucha, Arvind Rajawat
2015 International Journal of Embedded Systems and Applications  
In this paper, we have developed a list based task distribution model which is based on the attributes of the tasks of an application and computing platform.  ...  In this paper, an on chip HRCS computing platform is configured on Virtex 5 FPGA using Xilinx EDK.  ...  An on chip Heterogeneous Reconfigurable Computing System (HRCS) is constructed on Virtex 5 FPGA device for application execution.  ... 
doi:10.5121/ijesa.2015.5102 fatcat:bhqbfz76qzhjpa3lhcl2rjslju
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