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Transistor Degradations in Very Large-Scale-Integrated CMOS Technologies
[chapter]
2018
Very-Large-Scale Integration
Keywords: hot carrier injection (HCI), hot carrier degradation (HCD), hot carrier-resistant design, negative bias temperature instability (NBTI), reaction-diffusion (R-D) of hydrogen ...
The historical evolution of hot carrier degradation mechanisms and their physical models are reviewed and an energy-driven hot carrier aging model is verified that can reproduce 62-nm-gate-long hot carrier ...
Acknowledgements The author would like to express his appreciation for the device modeling and reliability group and the DRAM device group of SK hynix for providing valuable measurement data and discussions ...
doi:10.5772/intechopen.68825
fatcat:k7plbtzeyvamvi3rzof6btr4ne
SOI for digital CMOS VLSI: design considerations and advances
1998
Proceedings of the IEEE
The impact of floating-body in partially depleted devices on the circuit operation, stability, and functionality are addressed. ...
This paper reviews the recent advances of silicon-on-insulator (SOI) technology for complementary metal-oxide-semiconductor (CMOS) very-large-scale-integration memory and logic applications. ...
The parasitic bipolar effect also worsens while CMOS devices are degraded at an elevated temperature. ...
doi:10.1109/5.663545
fatcat:6lcb6y72k5hphoahsmutzgytbi
Superimposed In-Circuit Fault Mitigation for Dynamically Reconfigurable FPGAs
2017
2017 17th European Conference on Radiation and Its Effects on Components and Systems (RADECS)
total ionizing dose effects. ...
Tomsk Polytechnic University, 6 National Research Nuclear University "MEPhI", 7 Novosibirsk State University Radiation hardened bandgap voltage reference was designed using Verilog-A physical modeling of ...
Radiation induced degradation of widely used bipolar voltage comparators was investigated in wide temperature range from high to liquid nitrogen temperatures. ...
doi:10.1109/radecs.2017.8696242
fatcat:frcrfuza2fdstitbsjoda5sn4y
Ultra-thin nanograin polysilicon devices for hybrid CMOS-NANO integrated circuits
2007
Of course my first thought goes to Prof. Adrian Ionescu, who gave me the opportunity and the privilege to realize my PhD in his laboratory. ...
Laboratoire d'électronique générale 2 SECTION DE GÉNIE ÉLECTRONIQUE A mes parents Acknowledgements I would have been surely unable to finish my PhD without the great help of the numerous people that contributed ...
Room temperature electrical characterization". The co-integration of polySiNW and nMOSFET has no effect on the polySiNW electrical characteritics. ...
doi:10.5075/epfl-thesis-3722
fatcat:hqyihx5rubabxpudmenmitjo34