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Predicting CMOS speed with gate oxide and voltage scaling and interconnect loading effects

K. Chen, C. Hu, P. Fang, M.R. Lin, D.L. Wollesen
1997 IEEE Transactions on Electron Devices  
Sub-quarter micron MOSFET's and ring oscillators with 2.5-6 nm physical gate oxide thicknesses have been studied at supply voltages of 1.5-3.3 V.  ...  To confirm the new and models, sub-quarter micron CMOSFET's and ring oscillators were fabricated with gate oxide thicknesses of 2.5-5.9 nm and effective channel length down to 0.22 m and were characterized  ...  Value of constant " " should be larger than unity due to Miller effect and fringing capacitance.  ... 
doi:10.1109/16.641365 fatcat:ccu5elifffcjleiukg5k7vo77a

Performance Prospects of Fully-Depleted SOI MOSFET-Based Diodes Applied to Schenkel Circuit for RF-ID Chips

Yasuhisa Omura, Yukio Iida
2013 Circuits and Systems  
IIDA 174 efficiency for a low-frequency range using experimental d. c. characteristics of SOI-QD made from various SOI MOSFET's, and a. c. analyses of SOI-QD are conducted using a two-dimensional (2D)  ...  An a. c. analysis indicates that the fully-depleted condition should hold to suppress the floating-body effect for GHz-level RF applications of a quasi-diode. Y. OMURA, Y.  ...  This study is financially supported by Kansai University research grants, Grant-in-Aid for Joint Research (2004Research ( -2005. The authors wish to express their thanks to Mr. Takuta Tamura, Mr.  ... 
doi:10.4236/cs.2013.42024 fatcat:j36q4edm4bgctha4fu4pjmru4m

Parasitic Effects Affecting Responsivity of Sub-THz Radiation Detector Built of a MOSFET

P. Kopyt, B. Salski, J. Marczewski, P. Zagrajek, J. Lusakowski
2015 Journal of Infrared, Millimeter and Terahertz Waves  
In this paper, an analysis of parasitic elements that are found in all typical metaloxide-semiconductor field-effect transistors (MOSFETs) has been performed from a viewpoint of a designer of sub-THz radiation  ...  The full effective circuit model of the MOSFET has been employed to analyze the behavior of the detector when subjected to sub-THz radiation delivered through the Gate and Source pads.  ...  The detecting structure is typically integrated with some antenna printed on a thick dielectric substrate of relatively high dielectric constant (e.g., GaAa, Si) in order to improve the responsivity of  ... 
doi:10.1007/s10762-015-0188-y fatcat:t37grjb7yfcshjgil3d3avra2q

Perspectives of UTBB FD SOI MOSFETs for Analog and RF Applications [chapter]

Valeriya Kilchytska, Sergej Makovejev, Mohd Khairuddin Md Arshad, Jean-Pierre Raskin, Denis Flandre
2014 Functional Nanomaterials and Devices for Electronics, Sensors and Energy Harvesting  
control of short channel effects (SCE).  ...  on UNIBOND TM SOI wafers with either 25 or 10 nm-thick BOX.  ...  Université catholique de Louvain, Louvain-la-Neuve, Belgium for his assistance with high-frequency measurements setup.  ... 
doi:10.1007/978-3-319-08804-4_2 fatcat:tyfbvqltpjdvdixkl6mu2a4tqi

Mobility and transverse electric field effects in channel conduction of wrap-around-gate nanowire MOSFETs

A.K. Sharma, S.H. Zaidi, S. Lucero, S.R.J. Brueck, N.E. Islam
2004 IEE Proceedings - Circuits Devices and Systems  
Respondents should be aware that notwithstanding any other provision of law, no person shall be subject to any penalty for failing to comply with a collection of information if it does not display a currently  ...  Send comments regarding this burden estimate or any other aspect of this collection of information, including suggestions for reducing this burden to Department of Defense, Washington Headquarters Services  ...  Similarly a B60 nm gate oxide was grown on the slab gate devices in order to minimise any oxide capacitance (C ox ) effects in our final analysis.  ... 
doi:10.1049/ip-cds:20040993 fatcat:pp7gffogcfbapgfs7y3gzvyx7u

Carbon Nanotube Capacitors [chapter]

Mark M., Eric W.
2010 Cutting Edge Nanotechnology  
The MOSFET's gate serves as one electrode, and its source and drain regions serve as the second electrode. The gate dielectric serves as the capacitor dielectric.  ...  N r  (13) Since C Q is in units of F/unit length, the total quantum capacitance of each bundle face is again: Separation Distance, s (nm)   , Q Bundle Bundle Side Q C N hC  (14) With C Bundle in  ...  and operation is discussed in the last few chapters of the book.  ... 
doi:10.5772/8859 fatcat:qudjmnr3pvcvjj22fazjxjvtbq

A rigorous simulation based study of gate misalignment effects in gate engineered double-gate (DG) MOSFETs

Santunu Sarangi, Shiv Bhushan, Abirmoya Santra, Sarvesh Dubey, Satyabrata Jit, Pramod Kumar Tiwari
2013 Superlattices and Microstructures  
Gate Engineering Techniques High-k dielectric High-k/metal gates were introduced into mass production in 2007 by Intel in the 45 nm CMOS technology generation.  ...  In practice, DIBL can be calculated as follows: ) ( ) ( ) ( ) ( low V high V low V high V DIBL Th Th    where ) (high V Sub threshold slope The sub threshold slope is a characteristic of a MOSFET's  ...  With SSM there are no significant variations in threshold voltage due to high drain to source voltage.  ... 
doi:10.1016/j.spmi.2013.05.009 fatcat:vqfqomoinbebbngq4sazr7tbwu

Development of fully depleted back-illuminated charge-coupled devices

Christopher J. Bebek, Donald E. Groom, Stephen E. Holland, Armin Karcher, William F. Kolbe, Nick P. Palaio, Natalie A. Roe, Bojan T. Turko, Guobin Wang, James D. Garnett, James W. Beletic
2004 Optical and Infrared Detectors for Astronomy  
In addition, preliminary performance results for high-voltage compatible CCD's, including a 3512 × 3512, 10.5 µm pixel CCD for the proposed SuperNova Acceleration Probe project, are presented.  ...  The status of CCD development efforts at Lawrence Berkeley National Laboratory is reviewed.  ...  Power MOSFET's have similarities with fully depleted CCD's in that both require that a high voltage be applied to the backside of the device.  ... 
doi:10.1117/12.552295 fatcat:sy5ok6dqh5hxplfrquee3vihsa

2021 Index IEEE Transactions on Electron Devices Vol. 68

2021 IEEE Transactions on Electron Devices  
-that appeared in this periodical during 2021, and items from previous years that were commented upon or corrected in 2021.  ...  The primary entry includes the coauthors' names, the title of the paper or other item, and its location, specified by the publication abbreviation, year, month, and inclusive pagination.  ...  ., +, TED June 2021 2625-2632 Suppression of Gate Leakage Current in Ka-Band AlGaN/GaN HEMT With 5-nm SiN Gate Dielectric Grown by Plasma-Enhanced ALD.  ... 
doi:10.1109/ted.2021.3138305 fatcat:37sowz27xjc4bjhktlrldi2nja

Differential integrator pixel architecture for dark current compensation in CMOS image sensors

Marzieh Mehri Dehnavi, Yves Audet, Elham Khamsehashari
2016 2016 14th IEEE International New Circuits and Systems Conference (NEWCAS)  
Also I would like to thank to my colleagues at Microelectronics Research Group who were always there for me with countless help and constructive discussions.  ...  I would like to thank the members of my committee, Dr. Mohamad Sawan and Dr. Abdelaziz Trabelsi for taking time to review my work.  ...  The high-K gate dielectric reduces direct tunneling current and is required to control this component of the leakage current for low standby power devices [25] . 1-6-4 Sub-threshold Leakage (ISUB) Sub-threshold  ... 
doi:10.1109/newcas.2016.7604824 dblp:conf/newcas/DehnaviAK16 fatcat:kuxb2bhmrrc5lbxffxqwhafkza

CMOS LOW NOISE AMPLIFIER DESIGN FOR MICROWAVE AND MMWAVE APPLICATIONS (INVITED REVIEW)

Xue Jun Li, Yue-Ping Zhang
2018 Electromagnetic Waves  
This paper reviews recent advances in the design of low noise amplifier (LNA) in complementary metal oxide semiconductor (CMOS) technology for radio transceivers at microwave and millimeter wave (mmWave  ...  First, the evolution of wireless communication systems and CMOS technology are briefly revisited to highlight the requirements of an LNA design.  ...  As shown in Figure 23 , the series inductor L M , forms an artificial transmission line with the gate-source and source-bulk capacitances of transistor M 2 and with the drain-bulk and gate-drain capacitance  ... 
doi:10.2528/pier18012410 fatcat:dipxgzvgqjhfbp4rm33zqpyrli

Miniaturized Low-Voltage Power Converters With Fast Dynamic Response

David M. Giuliano, Matthew E. D'Asaro, Jacob Zwart, David J. Perreault
2014 IEEE Journal of Emerging and Selected Topics in Power Electronics  
The results are demonstrated in a 2.4 W dc-dc converter implemented in a 180 nm CMOS IC process and co-packaged with its passive components for high-performance.  ...  This thesis introduces a two-stage architecture that combines the strengths of switched capacitor (SC) techniques (small size, light-load performance) with the high efficiency and regulation capability  ...  This is a different situation than what happens when charging a MOSFET's gate capacitance.  ... 
doi:10.1109/jestpe.2014.2331671 fatcat:mkm7cphiznfwrp5vkqkquop6ru

Future trends in microelectronics - reflections on the road to nanotechnology

1997 Precision engineering  
the data needed, and completing and reviewing the collection of information.  ...  Send comment regarding this burden estimates or any other aspect of this collection of information, including suggestions for reducing this burden, to Washington Headquarters Services, Directorate for  ...  We consider such grating structures particularly promising for future applications, and extensive studies of such structures are currently underway, to be reported in due course.  ... 
doi:10.1016/0141-6359(97)90048-9 fatcat:j7blw4wn6zbitmoqqffj46g54e

System-level modeling and reliability analysis of microprocessor systems

Chang-Chih Chen, Linda Milor
2013 5th IEEE International Workshop on Advances in Sensors and Interfaces IWASI  
However with the introduction of high-k metal gate stacks for sub-45 nm technology nodes, degradation in NMOS devices due to positive bias has increased, with large degradation observed for both types  ...  More recently, because of the introduction of new materials (copper, low-k intra and inter-layer dielectrics, high-k gate dielectrics), the increase in the number of interconnect layers with smaller  ... 
doi:10.1109/iwasi.2013.6576097 dblp:conf/iwasi/ChenM13 fatcat:dafiu7whyfclvakbdnd3xy37gq

Quantum Transport in Semiconductor Nanostructures [chapter]

C.W.J. Beenakker, H. van Houten
1991 Solid state physics (New York. 1955)  
Adiabatic Transport (Edge Channels and the Quantum Hall Effect, Selective Population and Detection of Edge Channels, Fractional Quantum Hall Effect, Aharonov-Bohm Effect in Strong Magnetic Fields, Magnetically  ...  Introduction (Preface, Nanostructures in Si Inversion Layers, Nanostructures in GaAs-AlGaAs Heterostructures, Basic Properties). II.  ...  Both the spacing and the length of the gates were 100 nm.  ... 
doi:10.1016/s0081-1947(08)60091-0 fatcat:n5si3es6xzcipl7oy5dfwuc5dm
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