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17th IEEE East-West Design and Test Symposium

Yervant Zorian, Vladimir Hahanov, Svetlana Chumachenko, Eugenia Litvinova
2019 2019 IEEE International Test Conference (ITC)  
The IEEE East-West Design & Test Symposium was the first English-language scientific and technical event led by IEEE in the post-Soviet space after the collapse of the USSR.  ...  The experience of organizing a successful and attractive IEEE EWDT Symposium based on the moral, tolerant relations between potential and real participants, which collect and organize talented, constructive  ...  SUMMARY OF THE IEEE EWDTS HISTORY 1) IEEE East-West Design & Test Statistics for 17 years. Reports accepted -1498. AUTHORS -4377. Countries -78. Cities -198. Companies and Universities -341.  ... 
doi:10.1109/itc44170.2019.9000168 dblp:conf/itc/ZorianHCL19 fatcat:inz4vqtumreejodfvixgstdrpq

EWDTS 2020 TOC

2020 2020 IEEE East-West Design & Test Symposium (EWDTS)  
Kelekhsaev 305 Developing a Multiple Testing Procedure in the D-Posterior Approach using the R Software Environment Sergei Simushkin, Elena Fedotova 310 Relationship Between Base Frequency of the  ...  Belozerov 356 Bio-inspired Approach to Microwave Circuit Design Vladislav Ivanovich Danilchenko, Yevgenia Vladimirovna Danilchenko, Viktor Mikhailovich Kureichik 362 Automatic Identification of Appendiceal  ... 
doi:10.1109/ewdts50664.2020.9224804 fatcat:7376qksytbauda66nd4flrzn2a

Test suite consistency verification

Sergiy Boroday, Alexandre Petrenko, Andreas Ulrich
2008 Proceedings of IEEE East-West Design & Test Symposium (EWDTS'08)  
Test cases are themselves prone to errors, thus techniques and tools to validate tests are needed. In this paper, we suggest a method to check mutual consistency of tests in a test suite.  ...  The strategy to execute such tests is not necessarily known at design time of the test suite. Thus test suite consistency must be verified irrespective of the test execution strategy.  ...  The absence of any SUT output in a given state is modeled by a designated quiescence output [2] .  ... 
doi:10.1109/ewdts.2008.5580145 dblp:conf/ewdts/BorodayPU08 fatcat:kmibe7wmjrbuzm3gu5uvv4rgsy

Fault tolerance of decomposed PLAs

O. Keren, I. Levin
2010 2010 East-West Design & Test Symposium (EWDTS)  
Introduction The reliability of nanoelectronic systems becomes a critical bottleneck when they are utilized for the practical design.  ...  In this sense, the concept presented in [3] is analogous to the concept of designing immune communication systems.  ... 
doi:10.1109/ewdts.2010.5742040 dblp:conf/ewdts/KerenL10 fatcat:n7pdnpkhobedbfz7znlt6euzga

Temperature aware test scheduling by modified floorplanning

Indira Rawat, M.K. Gupta, Virendra Singh
2014 Proceedings of IEEE East-West Design & Test Symposium (EWDTS 2014)  
The temperature-aware design technique requires optimization in all phases of design. This paper, proposes an effective temperature-aware scheduling with incremental binding for the IC design.  ...  Thus, a power-aware High-Level Synthesis technique concentrates on the overall power reduction and is not appropriate for temperature-aware IC design.  ...  The floor planning creates the East J. Sci.  ... 
doi:10.1109/ewdts.2014.7027087 dblp:conf/ewdts/RawatGS14 fatcat:b7ft2tsnqjartpxnkslza5brkm

GA-based and design by contract approach to test generation for EFSMs

Andrey Zakonov, Oleg Stepanov, Anatoly Shalyto
2010 2010 East-West Design & Test Symposium (EWDTS)  
This paper proposes an approach for automated test generation for EFSM models. Design by contract approach is applied to formalize specification requirements.  ...  Design contracts are used to create models containing specification requirements. Genetic algorithm is used to automate the test generation process.  ...  Seamless integration of test creation into the development process would allow detecting possible implementation faults and design flaws at all development stages.  ... 
doi:10.1109/ewdts.2010.5742047 dblp:conf/ewdts/ZakonovSS10 fatcat:3tcicls3hndirjhxran3gpfahy

Constructing test sequences for hardware designs with parallel starting operations using implicit FSM models

Mikhail Chupilko
2010 2010 East-West Design & Test Symposium (EWDTS)  
{(A 1 , 1), (A 2 , 1), …, (A K , 1)} ∪ next(S, A) = {(A i , N i ) | pre(A i , N i ) = false} ∪ {(A i , N i + 1) | pre(A i , N i ) = true ∧ N i < N} Reducing code of test system more than to two times  ...  with the modern Open Verification Methodology (OVM) Constructing Multi-Stimuli 8 Stimuli from the test engine To the inputs of the DUT Buffer accumulator for stimuli CLK A A Buffer A  ... 
doi:10.1109/ewdts.2010.5742071 dblp:conf/ewdts/Chupilko10 fatcat:ce2esbha7zakja65ms5e52qei4

Deriving complete finite tests based on state machines

Igor Burdonov, Alexander Kossatchev, Nina Yevtushenko
2014 Proceedings of IEEE East-West Design & Test Symposium (EWDTS 2014)  
Many state machine based strategies return complete but infinite test suites. One solution for getting complete finite tests is to limit the number of faults, i.e., to consider a finite fault domain.  ...  In this paper, we summarize some results on deriving complete test suites w.r.t. infinite fault domains against proper types of the specification machines.  ...  A test case over input alphabet I and output alphabet O is an acyclic single-input output-complete FSM that can have a designated deadlock state fail [7] .  ... 
doi:10.1109/ewdts.2014.7027082 dblp:conf/ewdts/BurdonovKY14 fatcat:lhyubzibdzgnbey5m2baqfneaq

Component architecture with runtime type definition

E. M. Grinkrug, A. R. Shakurov
2010 2010 East-West Design & Test Symposium (EWDTS)  
The component-based approach to software design and development is being focused on.  ...  Although it's known for a fact the label is a subject to change only during design time (and at runtime it's constant), we have no means of expressing that.  ...  The first examples are program libraries, design patterns [4] and application frameworks. Objectoriented and generic programming [3] also contains this idea at its core.  ... 
doi:10.1109/ewdts.2010.5742123 dblp:conf/ewdts/GrinkrugS10 fatcat:y3hlappnnngpjpgqvbxeaqzjgm

Query optimization based on time scheduling approach

Wajeb Gharibi, Ayman Mousa
2013 East-West Design & Test Symposium (EWDTS 2013)  
. − Real queries are built to test as Q1, Q2, Q3, Q4, Q5, Q6, Q7, and Q8. These queries are varying in join the tables. A.  ... 
doi:10.1109/ewdts.2013.6673131 dblp:conf/ewdts/GharibiM13 fatcat:qtnqpn7q75hzxo7ujlebhmzh7m

Dynamic characteristics of different system design strategies

A. Zemliak, M. Torres, F. Reyes, S. Vergara, T. Markina
2010 2010 East-West Design & Test Symposium (EWDTS)  
The Lyapunov function of the design process was proposed to analyze the total design time.  ...  compose the structural design basis.  ...  Behavior of the functions V(t) and W(t) for four design strategies during the design process for network in Fig.1 ; (a) -initial part of the design process, (b) -design process the whole with the final  ... 
doi:10.1109/ewdts.2010.5742141 dblp:conf/ewdts/ZemliakTRVM10 fatcat:fju33oy5pjb6lhe2wzmygw26ta

System level hardware design and simulation with SystemAda

Negin Mahani, Parnian Mokri, Zainalabedin Navabi
2008 Proceedings of IEEE East-West Design & Test Symposium (EWDTS'08)  
Ada language has a structure which allows the design of systems to be expressed independently of its implementation and thus can be a good system design language for use with these techniques [1] .  ...  Many of these techniques produce design structures that are easily expressible in Ada language.  ...  With Kernel Ada, design can be integrated with testing, and an iterative design process can be greatly simplified [7] . The idea of using Ada as an HDL goes back to 1980's.  ... 
doi:10.1109/ewdts.2008.5580140 dblp:conf/ewdts/MahaniMN08 fatcat:hh2cnz443zeujnw4dgktxp7x3y

Metastability testing at FPGA circuit design using propagation time characterization

Branka Medved Rogina, Peter Skoda, Karolj Skala, Ivan Michieli, Maja Vlah, Sinisa Marijan
2010 2010 East-West Design & Test Symposium (EWDTS)  
The same test methods can also be used for evaluation of timing reliability in digital circuits as well.  ...  In order to demonstrate this testing approach, the results for metastable characteristics parameters of one FPGA digital circuit fabricated commercially in 90 nm CMOS process are presented.  ...  Logical connection of IOB and CLB test FFs in Spartan-3 FPGA for metastability test The time waveform diagram of reference signals for metastability test is shown in Fig. 6 . A.  ... 
doi:10.1109/ewdts.2010.5742050 dblp:conf/ewdts/RoginaSSMVM10 fatcat:wwnrqo6gtrh6pfnlab7ujh7cim

EDACs and test integration strategies for NAND flash memories

Stefano Di Carlo, Michele Fabiano, Roberto Piazza, Paolo Prinetto
2010 2010 East-West Design & Test Symposium (EWDTS)  
As a consequence a novel strategy integrating a particular codebased design environment with newly selected testing strategies is presented in this paper. 978-1-4244-9556-6/10/$26.00 ©2010 IEEE  ...  However also testing strategies need to be explored in order to provide highly dependable systems.  ...  The integration of EDAC and testing strategies practically leads to the design of a fault-tolerant system. Figure 1 shows an overview of the system integrating EDAC and test.  ... 
doi:10.1109/ewdts.2010.5742060 dblp:conf/ewdts/CarloFPP10a fatcat:hxuohiglovakfelfddmjcuusqy

Gyroscope explorer terrain angles classification

Christofer Yalung, Salah Al Majeed, Cid Mathew Adolfo, Jalal Karam, Lela Mirtskhulava
2016 2016 IEEE East-West Design & Test Symposium (EWDTS)  
The closer the curve comes to the 45-degree diagonal of the ROC space, the less accurate the test [21]. Fig. 6 . 6 Training ROC and Test ROC Fig. 7. Validate Roc and All ROC  ...  Significant research on intelligent wheelchairs has focused on the design and control aspects, including but not limited to human-machine interfaces and autonomous navigation [11] - [16] .  ... 
doi:10.1109/ewdts.2016.7807679 dblp:conf/ewdts/YalungAAKM16 fatcat:qcyqwhwyffcynfsbkmsbivkjsa
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