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Early probabilistic noise estimation for capacitively coupled interconnects

Murat R Becer, David Blaauw, Ibrahim N. Hajj, Rajendran Panda
2002 Proceedings of the 2002 international workshop on System-level interconnect prediction - SLIP '02  
Probabilistic Extraction Probabilistic estimation of coupling and ground capacitances using congestion information for each segment that a net traverses. How?  ...  : Per unit coupling and ground caps for a particular interconnect technology are characterized for a number of density configurations: Probabilistic Extraction After determining per unit length coupling  ... 
doi:10.1145/505348.505365 dblp:conf/slip/BecerBHP02 fatcat:rfufyn7oq5amladbzf5qfgrj5i

Early probabilistic noise estimation for capacitively coupled interconnects

Murat R Becer, David Blaauw, Ibrahim N. Hajj, Rajendran Panda
2002 Proceedings of the 2002 international workshop on System-level interconnect prediction - SLIP '02  
Probabilistic Extraction Probabilistic estimation of coupling and ground capacitances using congestion information for each segment that a net traverses. How?  ...  : Per unit coupling and ground caps for a particular interconnect technology are characterized for a number of density configurations: Probabilistic Extraction After determining per unit length coupling  ... 
doi:10.1145/505364.505365 fatcat:75asy27rx5eg7mhpnx4vuzvb2a

Early probabilistic noise estimation for capacitively coupled interconnects

M.R. Becer, D. Blaauw, R. Panda, I.N. Hajj
2003 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
Probabilistic Extraction Probabilistic estimation of coupling and ground capacitances using congestion information for each segment that a net traverses. How?  ...  : Per unit coupling and ground caps for a particular interconnect technology are characterized for a number of density configurations: Probabilistic Extraction After determining per unit length coupling  ... 
doi:10.1109/tcad.2002.807892 fatcat:cuzw2s5y7jhftaffbt3vbjclka

Power estimation techniques for FPGAs

J.H. Anderson, F.N. Najm
2004 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
We develop empirical prediction models for these parameters, suitable for use in power-aware layout synthesis, early power estimation/planning, and other applications.  ...  In this paper, we consider early prediction of net activity and interconnect capacitance in field-programmable gate array (FPGA) designs.  ...  Noise in Interconnect Capacitance To gauge the inherent noise in capacitance estimation, we take an approach similar to that used in [25] .  ... 
doi:10.1109/tvlsi.2004.831478 fatcat:oejkhsbwljbuzesubgchtbqieu

From blind certainty to informed uncertainty

Kurt Keutzer, Michael Orshansky
2002 Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems - TAU '02  
More fundamentally we believe that for circuits to be reliably designed the underlying probabilistic effects must be brought to the forefront of design and no longer hidden under conservative approximations  ...  ABSTRACT The accuracy, computational efficiency, and reliability of static timing analysis have made it the workhorse for verifying the timing of synchronous digital integrated circuits for more than a  ...  While it is possible to come up with the worst-case estimate for the active coupling capacitance, such estimates severely limit the design space because of their conservatism.  ... 
doi:10.1145/589411.589419 dblp:conf/tau/KeutzerO02 fatcat:f2vkixmlpnelffghweyqzgfyli

From blind certainty to informed uncertainty

Kurt Keutzer, Michael Orshansky
2002 Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems - TAU '02  
More fundamentally we believe that for circuits to be reliably designed the underlying probabilistic effects must be brought to the forefront of design and no longer hidden under conservative approximations  ...  ABSTRACT The accuracy, computational efficiency, and reliability of static timing analysis have made it the workhorse for verifying the timing of synchronous digital integrated circuits for more than a  ...  While it is possible to come up with the worst-case estimate for the active coupling capacitance, such estimates severely limit the design space because of their conservatism.  ... 
doi:10.1145/589418.589419 fatcat:abyqt4qbmbad7cvervw4v57sma

Full-chip verification of UDSM designs

R. Saleh, D. Overhauser, S. Taylor
1998 Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design - ICCAD '98  
The key issues of IR drops in the power grid, electromigration in power and signal lines, clock skew, signal coupling and its effect on timing and noise are described.  ...  This tutorial describes the problems encountered in typical ultra-deep submicron (UDSM) designs, and the full-chip interconnect verification methodologies needed to successfully identify these problems  ...  ACKNOWLEDGEMENTS The authors would like to thank Pete McCrorie, Michael Benoit, Steffen Rochel, Zakir Hussain, Greg Steele and Janet Greene for their contributions in putting this tutorial together.  ... 
doi:10.1145/288548.289070 dblp:conf/iccad/SalehOT98 fatcat:iruvweed3jfa5i5nga3h2hlvz4

FullChip Verification of UDSM Designs [chapter]

2009 Signal Integrity Effects in Custom IC and ASIC Designs  
The key issues of IR drops in the power grid, electromigration in power and signal lines, clock skew, signal coupling and its effect on timing and noise are described.  ...  This tutorial describes the problems encountered in typical ultra-deep submicron (UDSM) designs, and the full-chip interconnect verification methodologies needed to successfully identify these problems  ...  ACKNOWLEDGEMENTS The authors would like to thank Pete McCrorie, Michael Benoit, Steffen Rochel, Zakir Hussain, Greg Steele and Janet Greene for their contributions in putting this tutorial together.  ... 
doi:10.1109/9780470546413.ch27 fatcat:kptxox2ssbfuxmyghq6ju2niae

Genetic Algorithms and Particle Swarm Optimization Mechanisms for Through-Silicon Via (TSV) Noise Coupling

Khaoula Ait Belaid, H. Belahrach, H. Ayad, Ridha Ejbali
2021 Applied Computational Intelligence and Soft Computing  
In this paper, two intelligent methods which are GAs and PSO are used to model noise coupling in a Three-Dimensional Integrated Circuit (3D-IC) based on TSVs.  ...  They allow computing all the elements of the noise model, which helps to estimate the noise transfer function in the frequency and time domain in 3D complicated systems.  ...  can be used to estimate the noise coupling in the time domain. e rest of this paper is organized as follows.  ... 
doi:10.1155/2021/8830395 fatcat:mztlsnufgvaexgfg5rgoqhcd5i

An interconnect energy model considering coupling effects

Taku Uchino, Jason Cong
2001 Proceedings of the 38th conference on Design automation - DAC '01  
Index Terms-Coupling effects, interconnect energy model, power estimation. 0278-0070/02$17.00 © 2002 IEEE  ...  This paper presents an analytical interconnect energy model with consideration of coupling effects, including crosstalk and glitch, which are not adequately considered by the conventional (1 2) 2 model  ...  This makes it possible to estimate interconnect delay, noise, and power at the early design stages, provided we have accurate interconnect models.  ... 
doi:10.1145/378239.379022 dblp:conf/dac/UchinoC01 fatcat:t3xvbsqe7jfplexf57zfgl6b5a

An interconnect energy model considering coupling effects

T. Uchino, J. Cong
2002 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
Index Terms-Coupling effects, interconnect energy model, power estimation. 0278-0070/02$17.00 © 2002 IEEE  ...  This paper presents an analytical interconnect energy model with consideration of coupling effects, including crosstalk and glitch, which are not adequately considered by the conventional (1 2) 2 model  ...  This makes it possible to estimate interconnect delay, noise, and power at the early design stages, provided we have accurate interconnect models.  ... 
doi:10.1109/tcad.2002.1013890 fatcat:pdadzourlvbv7kyy3ddswzfsay

Statistical gate delay calculation with crosstalk alignment consideration

Andrew B. Kahng, Bao Liu, Xu Xu
2006 Proceedings of the 16th ACM Great Lakes symposium on VLSI - GLSVLSI '06  
., difference of signal arrival times in coupled neighboring interconnects. This effect is as significant as multiple-input switching on gate delay variation [2].  ...  We establish a functional relationship between driver gate delay and crosstalk alignment by deterministic circuit simulation, and derive closed form formulas for statistical distributions of driver gate  ...  A crosstalk aggressor signal switching injects a noise to the victim net, which leads to a changed effective load capacitance, and a variation of gate delay for the driver of the victim net.  ... 
doi:10.1145/1127908.1127961 dblp:conf/glvlsi/KahngLX06 fatcat:dkvyupcsxrcdplz6ltn5yqimhq

Power, Thermal, and Reliability Modeling in Nanometer-Scale Microprocessors

D. Brooks, R.P. Dick, R. Joseph, Li Shang
2007 IEEE Micro  
Node capacitance depends heavily on the actual design layout (including overlap and node-to-node coupling capacitances) and the supply voltage.  ...  Microarchitectural simulators with support for cycle-by-cycle power estimates can model the impact of mid-frequency inductive noise.  ... 
doi:10.1109/mm.2007.58 fatcat:gebuecbksrgthitqhcvrd2mp2e

Minimal-power, delay-balanced smart repeaters for interconnects in the nanometer regime

Roshan Weerasekera, Dinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen
2006 Proceedings of the international workshop on System-level interconnect prediction - SLIP'06  
When there is coupling between interconnects, the effective capacitance of a given wire is a function not only of the physical geometry, but also the relative switching pattern described by the bits on  ...  For a higher effective load capacitance both drivers switch, while for a lower effective capacitance the assistant driver is quiet.  ...  of the coupling capacitance  ... 
doi:10.1145/1117278.1117301 dblp:conf/slip/WeerasekeraPZT06 fatcat:lqbiwmuqirdaxach6kvhc4rsdu

Signal Integrity: Fault Modeling and Testing in High-Speed SoCs [chapter]

Mehrdad Nourani, Amir Attarha, Krishnendu Chakrabarty
2002 SOC (System-on-a-Chip) Testing for Plug and Play Test Automation  
In this paper, we first define a model for integrity faults on the high-speed interconnects.  ...  Then, we present a BIST-based test methodology that includes two special cells to detect and measure noise and skew occurring on the interconnects of the gigahertz system-on-chips.  ...  Acknowledgement The authors thank Nagaraj NS (Texas Instruments, Inc.) and Jerry Tallinger (OEA International, Inc.) for providing their simulator packages and helpful comments.  ... 
doi:10.1007/978-1-4757-6527-4_12 fatcat:cxgzdzhu3becxlez7t2kjuvfwe
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