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Comparison of ESP programming platforms
2021
Computer Science and Information Technologies
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Each of them is very specific and has different advantages. The programming style, efficiency, speed of execution, level of advancement, or memory usage will differ from one language to another. ...
They allow users to develop applications for ESP modules in different programming languages, such as C++, C, Lua, MicroPython, or using AT Commands. ...
Every language is very specific and has its outstanding features. ...
doi:10.11591/csit.v2i2.p77-86
fatcat:ennsp2zt2bc67hnvpzinfawvsq
Challenges in Implementing an ESP Service
[chapter]
2004
Lecture Notes in Computer Science
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We discuss engineering considerations for ESP in both low-end uniprocessor and higher-end network processor scenarios, and present performance measurements from both implementations. ...
For example, high-end routers and switches are designed to handle as many interfaces delivering packets at wire speed as possible; in such an environment decentralized processing, pipelining, and efficient ...
Router configuration with ESP the click authors, and found the time to process an IP packet to be roughly 1300 ns for a total forwarding rate of 765 Kpps. ...
doi:10.1007/978-3-540-24715-9_2
fatcat:vmp5jqua6bgdtpxfvkpzpolzr4
PONDERING LANGUAGE RIGHTS: A NOVELLA
2012
Espaço Jurídico
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The central argument of this article maintains that an onslaught on a particular language ordinarily emasculates the people who speak it. Keywords: Cultural rights. Language. Discrimination. Community ...
One would then fully visualize why the struggle for liberation must, alternatively and depending on the context, extol the virtues of pluralism, combat social subjugation, and pursue decolonization. ...
"It's been a long day for many of you and now it's time to go home." Nonetheless, we all hung out for a while in order to celebrate. The festivity lasted, full blast, for about an hour. ...
doaj:ad348609879d42e6ba9c96b6628818e3
fatcat:3lgflrv37vd6lidqlceg74pk5q
REASON-GIVING IN COURT PRACTICE: THE EXAMPLE OF FRENCH IMMIGRATION LITIGATION
2012
Espaço Jurídico
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Abstract: This Article examines the thesis according to which the practice of giving reasons for decisions is a central element of liberal democracies. ...
In the second case, reasons go beyond democracy because judges' ambitions are much greater than to merely provide petitioners with a ground for understanding and criticizing the decision: they aim at positively—and ...
Such actions need not even involve an attempt to control the behavior of the person. ...
doaj:5d7ba096c2df4a3d9249172441308380
fatcat:4uur2vycm5gotirdpj2gwcpwn4
High-level synthesis of accelerators in embedded scalable platforms
2016
2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC)
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Embedded scalable platforms combine a flexible socketed architecture for heterogeneous system-on-chip (SoC) design and a companion system-level design methodology. ...
An SoC is an instance of an ESP architecture that is obtained by specifying a mix of tiles. ...
Function encapsulation allows HLS to reduce the large number of states in the main module that may produce an inefficient circuit with a long critical path delay due to the complicated control; in addition ...
doi:10.1109/aspdac.2016.7428012
dblp:conf/aspdac/MantovaniGC16
fatcat:mc57dimmzvguljpga6z5ubdpse
Invited - The case for embedded scalable platforms
2016
Proceedings of the 53rd Annual Design Automation Conference on - DAC '16
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Embedded Scalable Platforms are a novel approach to SoC design and programming that addresses these design-complexity challenges by combining an architecture and a methodology. ...
The case for Embedded Scalable Platforms is made based on experiments on the development of various full-system prototypes and experience in teaching these concepts in a new graduate course. ...
For the design-entry point, the ESP methodology replaces RTL specifications in VHDL or Verilog with the use of SystemC, an IEEEstandard object-oriented language based on C++ [5, 18] . ...
doi:10.1145/2897937.2905018
dblp:conf/dac/Carloni16
fatcat:kybutezg4jdmpkqr6bldugxkzi
Pauli Error Propagation-Based Gate Reschedulingfor Quantum Circuit Error Mitigation
[article]
2022
arXiv
pre-print
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Our proposed approaches have been validated using a variety of quantum circuits with different success metrics, which are executed on IBM quantum computers. ...
While several compilation approaches have been proposed to minimize circuit errors, they often omit the detailed circuit structure information that does not affect the circuit depth or the gate count. ...
We thank IBM Quantum for the access to the IBM processors through the IBM Quantum Researchers Program. ...
arXiv:2201.12946v1
fatcat:tuz46dpeivduhfnjslph2zuo6a
An Innovative Wireless Sensor Network Protocol Implementation Using A Hybrid Fpga Technology
2011
Zenodo
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micro-controller architecture features are used; and the rapid obsolescence of micro-controller comparing to the long lifetime of power plants or any industrial installations. ...
The application of such approach is illustrated through the implementation of an innovative wireless sensor network protocol called OCARI. ...
In case of obsolescence of these circuits, they can be "transferred" to IPs and then IPs can be reused or adapted for specific need using VHDL. ...
doi:10.5281/zenodo.1070321
fatcat:zetmmbhfrjfntn6cdpb372nuyq
Pauli Error Propagation-Based Gate Rescheduling for Quantum Circuit Error Mitigation
2022
IEEE Transactions on Quantum Engineering
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For hybrid quantum algorithms, application-specific success criteria are used. ...
I + II (b)
TABLE 6 : 6 Run time of Prop. I, Prop. II, and Prop. I+II algorithms for QAOA circuits mapped to IBM Q16 Melbourne. Benc- Execution Time (msec) hmark hmark Prop. I Prop. II Prop. ...
ACKNOWLEDGEMENT We acknowledge the use of IBM Quantum services for this work. ...
doi:10.1109/tqe.2022.3161197
fatcat:xrcsjhq4treplchdazrstppwmy
Broadening the exploration of the accelerator design space in embedded scalable platforms
2017
2017 IEEE High Performance Extreme Computing Conference (HPEC)
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To address these limitations, we augmented the set of HLS knobs for ESP with three additional knobs, named eXtended Knobs (XKnobs). ...
HLS tools offer a powerful set of parameters, known as knobs, to optimize the architecture of an accelerator and evaluate different trade-offs in terms of performance and costs. ...
The ESP Architecture. The architecture of an ESP instance consists of a particular mix of tiles. ...
doi:10.1109/hpec.2017.8091091
dblp:conf/hpec/PiccolboniMGC17
fatcat:vjiejgyb6rekxgvv3surriu5oy
A practical bytecode interpreter for programmable routers on IXP network processors
2009
Computer Networks
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WASP provides safety with limited performance penalty through predictable execution time and bounded usage of memory and network resources. ...
We exploit lessons from past active network research and our knowledge of network processors to design a minimal interpreter that favours language restrictions over run-time checks. ...
Acknowledgements Sylvain Martin was a Research Fellow of the Belgian National Fund for Scientific Research (FNRS) and also partially funded by the EU under the ANA FET project (FP6-IST-27489). ...
doi:10.1016/j.comnet.2009.06.007
fatcat:qjxiqdmkcvclfdknnx476vgmjq
Secure Multiparty Computation and Trusted Hardware: Examining Adoption Challenges and Opportunities
2019
Security and Communication Networks
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Trusted execution environments (TEEs) provide hardware-enforced isolation of code and data in use, making them promising candidates for making SMC more tractable. ...
The traditional enabler of SMC is cryptography, but the significant number of cryptographic operations required results in these techniques being impractical for most real-time, online computations. ...
Acknowledgments Special thanks are due to Patrick Traynor and Thomas Shrimpton for their interest in and constructive criticisms of this work. ...
doi:10.1155/2019/1368905
fatcat:izynm6msrvehfa3ghkw7tykk34
Tutorial: Open-Source EDA and Machine Learning for IC Design: A Live Update
2020
2020 33rd International Conference on VLSI Design and 2020 19th International Conference on Embedded Systems (VLSID)
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Towards that goal, he investigates machine learning techniques (specifically, reinforcement learning) for optimizing EDA flows with no human in the loop. Abdelrahman received a ...
He mixes software industry experience with his research to reimagine the Electronic Design Automation (EDA) landscape. ...
He was a technical program chair (2016-2017), a symposium chair and an executive committee member for the Symposium on VLSI circuits, a technical program chair for Asian Solid-State Circuits Conference ...
doi:10.1109/vlsid49098.2020.00016
dblp:conf/vlsid/HosnyK20
fatcat:gsvvnrgbr5dpdjwkkx63jnf2f4
A Survey of Machine Learning for Computer Architecture and Systems
[article]
2021
arXiv
pre-print
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2021 accepted doi:10.1145/3494523 arXiv:2102.07952v2 fatcat:xevdv2ta2vapfop6k6cfbuihny
It has been a long time that computer architecture and systems are optimized to enable efficient execution of machine learning (ML) algorithms or models. ...
For ML-based modelling, we discuss existing studies based on their target level of system, ranging from the circuit level to the architecture/system level. ...
[238] coordinate an ANN controller with a proportional integral for uncore DVFS. ...
arXiv:2102.07952v1
fatcat:vzj776a6abesljetqobakoc3dq
Dynamic Simulation of Residential Buildings Supporting the Development of Flexible Control in District Heating Systems
2019
Proceedings Name
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We finally used the detailed simulator to test an optimal space-heating controller, thereby allowing many incremental improvements without jeopardizing endusers thermal comfort. ...
To ease the development of such an advanced controller, we programmed a detailed dynamic Modelica simulator representative of French multi-stories radiator-heated residential buildings. ...
Acknowledgements We gratefully acknowledge ADEME (Agence de l'Environnement et de la Maîtrise de l'Énergie) and the City-Zen project for their support and financial contribution in funding the Ph.D. thesis ...
doi:10.3384/ecp19157129
dblp:conf/modelica/AounBVBS19
fatcat:gcfc4gzcevgk5komfmapawocby
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