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ESL

Francine Bacchini, David Maliniak, Terry Doherty, Peter McShane, Suhas A. Pai, Sriram Sundararajan, Soo-Kwan Eo, Pascal Urard
2005 Proceedings of the 42nd annual conference on Design automation - DAC '05  
PANEL SUMMARY Electronic System-Level design has arrived -but can ESL provide the bridge from systems to silicon?  ...  Comprised of real world designers, this DAC ESL panel will examine and debate what works, what doesn't, and what the gaps are in the methodology and tool offerings.  ...  Soo-Kwan Eo, Samsung I believe that ESL bridges the economic gap between systems and silicon.  ... 
doi:10.1145/1065579.1065602 dblp:conf/dac/BacchiniMDMPSEU05 fatcat:s4hyigwwtbbkdha2hue2qqx73e

Formal ESL Synthesis for Control-Intensive Applications

Michael F. Dossis
2012 Advances in Software Engineering  
Due to the massive complexity of contemporary embedded applications and integrated systems, long effort has been invested in high-level synthesis (HLS) and electronic system level (ESL) methodologies to  ...  This work surveys and reviews past and current research in the area of ESL and HLS.  ...  This work intends to bridge the gap in design implementation quality between HLS results from dataflowdominated descriptions, and those from conditional controlflow-dominated source models.  ... 
doi:10.1155/2012/156907 fatcat:f55w3dv6crflzfqinksfrcahnu

OpenRISC System-on-Chip Design Emulation [article]

Kai Cong, Li Lei, Zhenkun Yang, Fei Xie
2016 arXiv   pre-print
To fully evaluate the powerfulness of the emulation approach and demonstrate its potential impact, we propose to emulate a system-on-chip (SoC) design using Mentor Graphics Veloce emulation platform.  ...  Recently the hardware emulation technique has emerged as a promising approach to accelerating hardware verification/debugging process.  ...  The major challenge of this research is to bridge the huge semantic gap between the ESL and RTL descriptions, which makes the direct comparison of designs in ESL and RTL difficult.  ... 
arXiv:1602.03095v1 fatcat:pdrhs6mbjzelzfswzq5crh3u5m

A New Design Methodology for Composing Complex Digital Systems

S.L. Chu, M.J. Lo
2013 Journal of Applied Research and Technology  
The functionalities of the used SOC chips and silicon intelligent properties in these portable devices are become complicated and hard to design.  ...  This paper proposed a new design methodology of digital system, called data-oriented methodology, to deal with the above problems, by using Bluespec SystemVerilog HDL and the corresponding tools.  ...  Acknowledgements This work is supported in part by the National Science Council of Republic of China, Taiwan under Grant NSC 101-2221-E-033-049.  ... 
doi:10.1016/s1665-6423(13)71529-3 fatcat:27xhpwe5mrgjbaftriqlnsfk6m

DAC Highlights

Sachin Sapatnekar, Leon Stok
2007 IEEE Design & Test of Computers  
Design for manufacturability (DFM) issues were prominent throughout the program, in the form of regular sessions on process-aware physical design, statistical timing analysis, bridging the gap with silicon  ...  This year's sessions were on topics such as trusted hardware, ESL verification, silicon measurement correlations, novel interconnect schemes, synthetic biology, and thousand-core chips.  ... 
doi:10.1109/mdt.2007.160 fatcat:gkxgpfr7cje2po4q7ptbku6p3q

Industrial IP integration flows based on IP-XACT standards

W. Kruijtzer, P. van der Wolf, E. de Kock, J. Stuyt, W. Ecker, A. Mayer, S. Hustin, C. Amerijckx, S. de Paoli, E. Vaumorin
2008 2008 Design, Automation and Test in Europe  
Further, we report on two future extensions to IP-XACT that are currently being explored in the SPRINT project, i.e.  ...  Effective integration of advanced Systems-on-Chip (SoC) requires extensive reuse of IP modules as well as automation of the IP integration process, including verification.  ...  IP Integration flow of NXP We present the IP-XACT-based IP integration flow for Electronic System Level (ESL) design and mixed RTL and ESL design in use in NXP.  ... 
doi:10.1109/date.2008.4484656 dblp:conf/date/KruijtzerWKSEMHAPV08 fatcat:lhzydcovpvdanbfjc24t7jx64e

Industrial IP integration flows based on IP-XACT#8482; standards

Wido Kruijtzer, Emmanuel Vaumorin, Pieter van der Wolf, Erwin de Kock, Jan Stuyt, Wolfgang Ecker, Albrecht Mayer, Serge Hustin, Christophe Amerijckx, Serge de Paoli
2008 Proceedings of the conference on Design, automation and test in Europe - DATE '08  
Further, we report on two future extensions to IP-XACT that are currently being explored in the SPRINT project, i.e.  ...  Effective integration of advanced Systems-on-Chip (SoC) requires extensive reuse of IP modules as well as automation of the IP integration process, including verification.  ...  IP Integration flow of NXP We present the IP-XACT-based IP integration flow for Electronic System Level (ESL) design and mixed RTL and ESL design in use in NXP.  ... 
doi:10.1145/1403375.1403386 fatcat:go43m4sgdzcoxizjgyezh2l3ta

Improving high frequency DC-DC converter performance with monolithic half bridge GaN ICs

David Reusch, Johan Strydom, John Glaser
2015 2015 IEEE Energy Conversion Congress and Exposition (ECCE)  
Experimental results for a 12 V IN to 1 V OUT buck converter operating at a switching frequency of 1 MHz and up to 40 A of output current will be demonstrated with 30 V eGaN monolithic half bridge (HB)  ...  The rapid maturation of GaN power transistors continues to enable new capabilities in high frequency power conversion.  ...  The most common building block used in power conversion is the half bridge. This therefore becomes the starting point for the journey towards a power system-on-achip.  ... 
doi:10.1109/ecce.2015.7309713 fatcat:vh6gvoyhczeqvk2dwr3ky4ojny

Enabling heterogeneous cycle-based and event-driven simulation in a design flow integrated using the SPIRIT consortium specifications

Chulho Shin, Peter Grun, Nizar Romdhane, Christopher Lennard, Gabor Madl, Sudeep Pasricha, Nikil Dutt, Mark Noll
2007 Design automation for embedded systems  
design, and the flow from ESL design to implementation has to be seamless.  ...  They also provide a virtual representation of the system on which embedded software development can commence prior to the availability of silicon [19] [20] [21] .  ...  as a key challenge to build a complex SoC virtual platform.  ... 
doi:10.1007/s10617-007-9003-x fatcat:ewdww5lwnvc4tinvf5an2fy3ae

Creation and utilization of a virtual platform for embedded software optimization:

Sungpack Hong, Jeongeun Kim, HoonSang Jin, Kyu-Myung Choi, Jeong-Taek Kong, SooKwan Eo, Sungjoo Yoo, Sheayun Lee, Sangwoo Lee, Hye Jeong Nam, Bum-Seok Yoo, Jaehyung Hwang (+2 others)
2006 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis - CODES+ISSS '06  
Virtual platform (ViP), or ESL (Electronic System Level) simulation model, is one of the most widely renowned system level design techniques.  ...  However, in our case study, we found that the current ViP technique needs further improvements to become a true ESL design technique.  ...  Introduction Virtual platform (ViP), or ESL (Electronic System Level) simulation environment, is one of the most widely renowned system level design techniques [1] .  ... 
doi:10.1145/1176254.1176311 dblp:conf/codes/HongYLLNYHSKKJCKE06 fatcat:6dfav7ordvfabk62ooxfiucgrm

Thermal phenomena in LTCC sensor structures

Marina Santo Zarnik, Franc Novak, Gregor Papa
2019 Sensors and Actuators A-Physical  
The simulations showed the same trends as the experimental measurements, which confirmed the assumed manifestation of the thermal phenomena.  ...  In most cases, replacement of the medium in direct contact with the sensing structure can critically affect the sensor's response.  ...  Acknowledgement The authors acknowledge the financial support from the Slovenian research agency (research core funding No. P2-0098).  ... 
doi:10.1016/j.sna.2019.02.031 fatcat:pqedeyxg5rdk7cqspum6dq3llu

A low-temperature co-fired ceramic micro-reactor system for high-efficiency on-site hydrogen production

Bo Jiang, Thomas Maeder, Alejandro J. Santis-Alvarez, Dimos Poulikakos, Paul Muralt
2015 Journal of Power Sources  
The output flow is sufficiently high to drive an optimized single membrane mSOFC cell of about the same footprint as the micro reactor.  ...  h i g h l i g h t s Novel high-temperature micro reaction system based on the LTCC technology. Demonstrated on-site, self sustained syngas production for micro SOFC applications.  ...  Acknowledgements The authors would like to thank Robert Büchel (ETHZ) for providing catalyst materials, and the Swiss National Science Foundation (contracts CRSI11_126830 and 200021_143424) for funding  ... 
doi:10.1016/j.jpowsour.2014.09.084 fatcat:d52unhjh5fgavjp3jtjhiy3u5a

Recent Developments in Configurable and Extensible Processors

Grant Martin
2006 IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06)  
It also discusses some of our future evolution -in particular, the move from a single processor focus to a multi-processor SoC (MPSoC) focus.  ...  There have been some interesting technology developments in the area of configurable and extensible processors in the last few years.  ...  XPRES technology has had three key impacts on the design methodology: Improved Design Methodologies The last few years have seen the real beginnings of an electronic system level (ESL) or system-level  ... 
doi:10.1109/asap.2006.57 dblp:conf/asap/Martin06 fatcat:xymdcs3kyrd7bcnb5h56wc3h5u

Virtual Prototyping Platform for Multiprocessor System-on-Chip Hardware/Software Co-design and Co-verification [chapter]

Arya Wicaksana, Tang Chong Ming
2017 Studies in Computational Intelligence  
One approach is to raise the abstraction level of system design and verification to ESL.  ...  The holy grail is to be able to verify the hardware design and synthesize to the gate level for physical layout, at the same time carry out software development for the hardware design using the same system  ...  Acknowledgements My deepest gratitude to my supervisor Mr. Tang Chong Ming, Prof. Lee Sze Wei, and Mr.  ... 
doi:10.1007/978-3-319-60170-0_7 fatcat:b652rfjyznhehe4xf3lfrygche

Design and Run-time Reliability at the Electronic System Level

Björn Sander, Andreas Bernauer, Wolfgang Rosenstiel
2010 IPSJ Transactions on System LSI Design Methodology  
Because of complexity reasons, the Electronic System Level (ESL) is gaining importance as starting point of design.  ...  The ongoing scaling of CMOS technology facilitates the design of systems with continuously increasing functionality but also raises the susceptibility of these systems to reliability issues.  ...  It was highlighted that the gap between the target applications and the correct modeling of physical effects has to be bridged at the electronic system level.  ... 
doi:10.2197/ipsjtsldm.3.140 fatcat:rjyitucncvb4baj2hzjm5twg7u
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