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Dynamically reducing overestimated design margin of MultiCores

Toshinori Sato, Takanori Hayashida, Ken Yano
2012 2012 International Conference on High Performance Computing & Simulation (HPCS)  
The combination of DVS (Dynamic voltage scaling) technique and Canary FF (flip-flop), named Canary-DVS, has been proposed to eliminate the overestimated voltage margin but has only been evaluated under  ...  They require large design margins in the supply voltage, resulting in large energy consumption.  ...  The authors would like to thank Shunitsu Kohara of Toshiba Corporation for helping them use MeP simulator.  ... 
doi:10.1109/hpcsim.2012.6266944 dblp:conf/ieeehpcs/SatoHY12 fatcat:6fehue5wrnaznnd3pdg6aqhtai

Multicore energy reduction utilizing canary FF

Yoshimi Otsuka, Toshinori Sato, Takahito Yoshiki, Takanori Hayashida
2010 2010 10th International Symposium on Communications and Information Technologies  
This paper proposes to utilize a dual-sensing flip-flop (FF), named Canary FF, in order to reduce the overestimated voltage margin.  ...  MultiCore Processor System-on-Chip (MPSoC) is one of the promising technique to satisfy computing demands of the future consumer devices.  ...  The authors would like to thank Shunitsu Kohara of Toshiba for helping them use MeP simulators.  ... 
doi:10.1109/iscit.2010.5665119 fatcat:4lof2c6oxjdvlnmh6pjlvjp5ca

Automatic TLM Generation for Early Validation of Multicore Systems

Samar Abdi, Yonghyun Hwang, Lochi Yu, Gunar Schirner, Daniel D. Gajski
2011 IEEE Design & Test of Computers  
These benefits come at the cost of higher design complexity, however, which makes design with conventional cycle-accurate models impractical.  ...  Designers are using transaction-level models (TLMs) as virtual platforms for early design validation and software development, although TLM development for multicore platforms can be timeconsuming and  ...  To fit the design on the board, we reduced the MP3 decoder test data to a single frame.  ... 
doi:10.1109/mdt.2010.117 fatcat:2qqiwsbz25brljryy37pbe7fea

A single processor approach for loosely synchronized execution of parallel flows on heterogeneous multicore

Stephane Louise, Vincent David, Fabien Calcado
2011 Procedia Computer Science  
by a kind of generalization of the superscalar design.  ...  From these observations, we investigated how to use multicore in a fashion that would be as close as possible as single processor programming, at least from the program design and debug point of view,  ...  As part of future work, we want to show that the ease to implement heterogeneous computing at low level can be translated as a way to easily implement a parallel compiler for this heterogeneous multicore  ... 
doi:10.1016/j.procs.2011.04.218 fatcat:evzizvqdandzxlmfzqdabc3mxi

Feedback thermal control of real-time systems on multicore processors

Yong Fu, Nicholas Kottenstette, Chenyang Lu, Xenofon D. Koutsoukos
2012 Proceedings of the tenth ACM international conference on Embedded software - EMSOFT '12  
RT-MTC dynamically enforces both the desired temperature set point and the schedulable CPU utilization bound of a multicore processor through DVFS.  ...  This paper presents Real-Time Multicore Thermal Control (RT-MTC), a novel feedback thermal control framework specifically designed for multicore real-time systems.  ...  The research of Nicholas Kottenstette and Xenofon Koutsoukos is supported in part by NSF Award NSF-CCF-0820088.  ... 
doi:10.1145/2380356.2380379 dblp:conf/emsoft/FuKLK12 fatcat:tdp5rqcod5dh5ecftd5mpqpoyi

ParaDox: Eliminating Voltage Margins via Heterogeneous Fault Tolerance

Sam Ainsworth, Lionel Zoubritzky, Alam Mycroft, Timothy M. Jones
2021 2021 IEEE International Symposium on High-Performance Computer Architecture (HPCA)  
This leads to very large margins on voltage and frequency, designed to avoid errors even in the worst case, along with significant hardware expenditure on eliminating voltage spikes and other forms of  ...  We estimate that compared to a non-resilient system with margins, ParaDox can reduce energy-delay product by 15% through undervolting, while completely recovering from any induced errors.  ...  There are other reasons for dynamically adjusting the level of sub-margin voltage we are willing to accept.  ... 
doi:10.1109/hpca51647.2021.00051 fatcat:6emtqh72dbbi7cnnkiiiaggmqu

On the Combination of Argumentation Solvers into Parallel Portfolios [chapter]

Mauro Vallati, Federico Cerutti, Massimiliano Giacomin
2017 Lecture Notes in Computer Science  
In particular, four methodologies aim at combining solvers in static portfolios, while two methodologies are designed for the dynamic configuration of parallel portfolios.  ...  Our empirical results demonstrate that the configuration of parallel portfolios is a fruitful way for exploiting multicore machines, and that the presented approaches outperform the state of the art of  ...  Acknowledgement The authors would like to acknowledge the use of the University of Huddersfield Queensgate Grid in carrying out this work.  ... 
doi:10.1007/978-3-319-63004-5_25 fatcat:mccwklzg2baphciqzq7b62budi

Structural properties of magnetic nanoparticles determine their heating behavior - an estimation of the in vivo heating potential

Robert Ludwig, Marcus Stapf, Silvio Dutz, Robert Müller, Ulf Teichgräber, Ingrid Hilger
2014 Nanoscale Research Letters  
In this study, the included MNP exhibited varying physicochemical properties and were either made up of single cores or multicores.  ...  Whereas the single core MNP exhibited a core size of approximately 15 nm, the multicore MNP consisted of multiple smaller single cores (5 to 15 nm) with 65 to 175 nm diameter in total.  ...  Acknowledgements The described work was carried out within the projects 'Multifunctional Nanoparticles for the Selective Detection and Treatment of Cancer' (MultiFun), which is funded by the European Seventh  ... 
doi:10.1186/1556-276x-9-602 pmid:25404872 pmcid:PMC4230907 fatcat:3nrteixjujazjdjpxlf7yruhxe

Flicker

Paula Petrica, Adam M. Izraelevitz, David H. Albonesi, Christine A. Shoemaker
2013 Proceedings of the 40th Annual International Symposium on Computer Architecture - ISCA '13  
To exploit Flicker's flexible pipeline architecture, a new online multicore optimization algorithm combines reduced sampling techniques, application of response surface models to online optimization, and  ...  This paper presents Flicker, a general-purpose multicore architecture that dynamically adapts to varying and potentially stringent limits on allocated power.  ...  While cores are homogeneous in design, they can be dynamically reconfigured into a heterogeneous multicore system that meets power constraints.  ... 
doi:10.1145/2485922.2485924 dblp:conf/isca/PetricaIAS13 fatcat:j5g2aj4kybcwdcyukk3ripmifa

Flicker

Paula Petrica, Adam M. Izraelevitz, David H. Albonesi, Christine A. Shoemaker
2013 SIGARCH Computer Architecture News  
To exploit Flicker's flexible pipeline architecture, a new online multicore optimization algorithm combines reduced sampling techniques, application of response surface models to online optimization, and  ...  This paper presents Flicker, a general-purpose multicore architecture that dynamically adapts to varying and potentially stringent limits on allocated power.  ...  While cores are homogeneous in design, they can be dynamically reconfigured into a heterogeneous multicore system that meets power constraints.  ... 
doi:10.1145/2508148.2485924 fatcat:qirtoj5fvrh2xnuzsqtgveiwai

A Survey on Cache Management Mechanisms for Real-Time Embedded Systems

Giovani Gracioli, Ahmed Alhammad, Renato Mancuso, Antônio Augusto Fröhlich, Rodolfo Pellizzoni
2015 ACM Computing Surveys  
One of the main factors for unpredictability in a multicore processor is the cache memory hierarchy.  ...  Multicore processors are being extensively used by real-time systems, mainly because of their demand for increased computing power.  ...  Suhendra and Mitra (this work was discussed in Section 3) were the first authors to evaluate the combination of cache partitioning and cache locking in the context of multicore real-systems [Suhendra  ... 
doi:10.1145/2830555 fatcat:nckhashqprghfnbcaqqu7vk5vi

Seeking Time-Composable Partitions of Tasks for COTS Multicore Processors

Gabriel Fernandez, Jaume Abella, Eduardo Quinones, Luca Fossati, Marco Zulianello, Tullio Vardanega, Francisco J. Cazorla
2015 2015 IEEE 18th International Symposium on Real-Time Distributed Computing  
The much-sought property of time composability [28], [15] , when transposed to a multicore processor, stipulates that the timing behavior of an individual task is not affected by the activity of its co-runners  ...  The advent of multicore processors challenges the viability of this two-step approach because several complex contention effects at the processor level arise that cause tasks to be unable to make progress  ...  This work has also been partially supported by the Spanish Ministry of Science and Innovation under grant TIN2012-34557.  ... 
doi:10.1109/isorc.2015.43 dblp:conf/isorc/FernandezAQFZVC15 fatcat:zbxdavl4nnarze5frhrkyckf7e

Seeking Time-Composable Partitions Of Tasks For Cots Multicore Processors

Gabriel Fernandez, Jaume Abella, Eduardo Qui˜nones, Luca Fossati, Marco Zulianello, Tullio Vardanega, Francisco J. Cazorla
2015 Zenodo  
The advent of multicore processors challenges the viability of this two-step approach because several complex contention effects at the processor level arise that cause tasks to be unable to make progress  ...  attributes of the individual tasks, including the ETB, are studied from the system level perspective.  ...  This work has also been partially supported by the Spanish Ministry of Science and Innovation under grant TIN2012-34557.  ... 
doi:10.5281/zenodo.55525 fatcat:6xsqiwfjjjhvdjhxzskj7qkuby

Virtual Timing Isolation for Mixed-Criticality Systems

Johannes Freitag, Sascha Uhrig, Theo Ungerer, Marc Herbstritt
2018 Euromicro Conference on Real-Time Systems  
If the slowdown exceeds the acceptable bounds, interferences will be reduced by controlling the behavior of low-critical cores to keep the main application's progress inside the given bounds.  ...  Commercial of the shelf multicore processors suffer from timing interferences between cores which complicates applying them in hard real-time systems like avionic applications.  ...  For example, a closed loop controller is used in [19] for dynamic resource allocation and power optimization of multicore processors.  ... 
doi:10.4230/lipics.ecrts.2018.13 dblp:conf/ecrts/FreitagUU18 fatcat:4732xtv3pfaqjn556k5akn4o3e

Architecture implications of pads as a scarce resource

Runjie Zhang, Ke Wang, Brett H. Meyer, Mircea R. Stan, Kevin Skadron
2014 2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA)  
is and will remain a critical problem for architects and circuit designers alike.  ...  ., C4 pads) between power supply and I/O, and the loss of such resources to electromigration, means that constructing a power delivery network (PDN) that satisfies noise margins without compromising performance  ...  Such techniques address a key weakness of dynamic margin adaptation: false positives where noise reduces timing margin but would not ultimately cause an error.  ... 
doi:10.1109/isca.2014.6853199 dblp:conf/isca/ZhangWMSS14 fatcat:yruivsyndbapvmp4izc3sbsc34
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