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Dynamically variable line-size cache exploiting high on-chip memory bandwidth of merged DRAM/logic LSIs

K. Inoue, K. Kai, K. Murakami
1999 Proceedings Fifth International Symposium on High-Performance Computer Architecture  
This paper proposes a novel cache architecture suitable for merged DRAM/logic LSIs, which is called "dynamically variable line-size cache (D-VLS cache)".  ...  The D-VLS cache can optimize its line-size according to the characteristic of programs, and attempts to improve the performance by exploiting the high on-chip memory bandwidth.  ...  Introduction For merged DRAM/logic LSIs with a memory hierarchy including cache memory, we can exploit high on-chip memory bandwidth by means of replacing a whole cache line at a time on cache misses  ... 
doi:10.1109/hpca.1999.744366 dblp:conf/hpca/InoueKM99 fatcat:iywerbf7vnbota3q4euwip3mzu

Performance/Energy Efficiency of Variable Line-Size Caches for Intelligent Memory Systems [chapter]

Koji Inoue, Koji Kai, Kazuaki Murakami
2001 Lecture Notes in Computer Science  
For merged DRAM/logic LSIs having on-chip cache memory, we can exploit the high bandwidth by means of replacing a whole cache line at a time.  ...  Introduction Integrating main memory (DRAM) and processors into a single chip, or merged DRAM/logic LSI, makes it possible to exploit high on-chip memory bandwidth by widening on-chip bus and on-chip DRAM  ... 
doi:10.1007/3-540-44570-6_13 fatcat:3yu5alibszasxd54k3iy65uixq