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Dynamic programming in faulty memory hierarchies (cache-obliviously)
2011
Foundations of Software Technology and Theoretical Computer Science
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In this paper we investigate the design of dynamic programming algorithms in faulty memory hierarchies. ...
Due to technological constraints, caches in the memory hierarchy of modern computer platforms appear to be particularly prone to bit flips. ...
We investigate the design of dynamic programming algorithms in the hierarchical faulty memory model. ...
doi:10.4230/lipics.fsttcs.2011.433
dblp:conf/fsttcs/CaminitiFFS11
fatcat:4jcx3auq7fhbvcrwq6dsapytge
Multi-Layer Memory Resiliency
2014
Proceedings of the The 51st Annual Design Automation Conference on Design Automation Conference - DAC '14
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Two specific exemplars are used to illustrate multilayer memory resilience: first we describe static and dynamic policies to achieve energy savings in caches using aggressive voltage scaling combined with ...
disabling faulty blocks; and second we show how software characteristics can be exposed to the architecture in order to mitigate the aging of large register files in GPGPUs. ...
A significant body of research exists on the design of a reliable memory hierarchy comprising multiple levels of caches and main memory. ...
doi:10.1145/2593069.2596684
dblp:conf/dac/DuttGNBGS14
fatcat:v6rb7n5m5bfj5gbbgloksy7ckq
Resilient Dynamic Programming
2015
Algorithmica
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We investigate the design of dynamic programming algorithms in unreliable memories, i.e., in the presence of errors that lead the logical state of some bits to be read differently from how they were last ...
The recursive algorithms are also cacheefficient and can tolerate faults at any level of the memory hierarchy. ...
To the best of our knowledge, no algorithms that are both resilient and cache-efficient across the entire memory hierarchy, in the spirit of cache-oblivious algorithms [30] , are known in the literature ...
doi:10.1007/s00453-015-0073-z
fatcat:c6lzvh2ahnd4lfulgxseys6qha
Algorithms and Data Structures
[chapter]
2009
Practical Guide to Computer Simulations
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Memory transfers occurring between consecutive levels of the memory hierarchy in modern computers are modeled in the I/O model and cache oblivious model, and the complexity of algorithms is given by the ...
The hardware factors affecting the running time that we consider include branch mispredictions occurring in the processor, memory transfers occurring between consecutive levels of the memory hierarchy ...
memory hierarchy. ...
doi:10.1142/9789812836632_0004
fatcat:5w2ix5xm35he7hv4oliyxcckzm
Algorithms and Data Structures
[chapter]
2008
Robustness and Usability in Modern Design Flows
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Memory transfers occurring between consecutive levels of the memory hierarchy in modern computers are modeled in the I/O model and cache oblivious model, and the complexity of algorithms is given by the ...
The hardware factors affecting the running time that we consider include branch mispredictions occurring in the processor, memory transfers occurring between consecutive levels of the memory hierarchy ...
memory hierarchy. ...
doi:10.1007/978-1-4020-6536-1_3
fatcat:vksli6i5wjgfbfrg3ifeqxlkeu
Algorithms and data structures
[chapter]
2015
Big Practical Guide to Computer Simulations
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Memory transfers occurring between consecutive levels of the memory hierarchy in modern computers are modeled in the I/O model and cache oblivious model, and the complexity of algorithms is given by the ...
The hardware factors affecting the running time that we consider include branch mispredictions occurring in the processor, memory transfers occurring between consecutive levels of the memory hierarchy ...
memory hierarchy. ...
doi:10.1142/9789814571784_0006
fatcat:i772srdlu5eq5eeoiqqytutg34
D2.1 Models for energy consumption of data structures and algorithms
[article]
2018
arXiv
pre-print
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It reports the early results of Task 2.1 on investigating and modeling the trade-off between energy and performance in concurrent data structures and algorithms, which forms the basis for the whole work ...
Relaxed cache-oblivious model and dynamic vEB layout We define relaxed cache oblivious algorithms to be cache-oblivious (CO) algorithms with the restriction that an upper bound U B on the unknown memory ...
Therefore without knowing anything about memory level hierarchy and the size of each level, a cache-oblivious algorithm can automatically adapt to multiple levels of the memory hierarchy. ...
arXiv:1801.09992v2
fatcat:3swp2g6mpzgvvowt7qoghlfhva
A Survey of Emerging Architectural Techniques for Improving Cache Energy Consumption
2016
Communications on Applied Electronics
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A lot of research effort has been put on finding techniques that can improve the energy efficiency of cache architectures. ...
in material negative system performance. ...
This memory hierarchy contribute largely in the energy consumption of the overall hardware/software architecture. ...
doi:10.5120/cae2016652443
fatcat:hvi6m63qaredfeg3dzecvjws2e
The Cray BlackWidow
2007
Proceedings of the 2007 ACM/IEEE conference on Supercomputing - SC '07
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The system supports thousands of outstanding references to hide remote memory latencies, and provides a rich suite of built-in synchronization primitives. ...
The system supports common programming models such as MPI and OpenMP, as well as global address space languages such as UPC and CAF. ...
Memory Hierarchy Each BW processor has a 16KB L1 data cache, a 16KB instruction cache, and a 512 KB unified L2 cache. The L1 cache is 2-way associative, and used only for scalar memory references. ...
doi:10.1145/1362622.1362646
dblp:conf/sc/AbtsBSFSLJBS07
fatcat:rryh3wefojaqjov3hmkshdf3na
Algorithm Engineering: Concepts and Practice
[chapter]
2010
Experimental Methods for the Analysis of Optimization Algorithms
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Over the last years the term algorithm engineering has become wide spread synonym for experimental evaluation in the context of algorithm development. Yet it implies even more. ...
We discuss the major weaknesses of traditional "pen and paper" algorithmics and the ever-growing gap between theory and practice in the context of modern computer hardware and real-world problem instances ...
, and it is therefore sufficient to analyze cache-oblivious algorithms using a two-level hierarchy without compromising their performance on a deeper hierarchy. ...
doi:10.1007/978-3-642-02538-9_6
fatcat:vamy6fe7rvfajdqp2n2k636ani
Architectural Techniques for Improving the Power Consumption of NoC-Based CMPs: A Case Study of Cache and Network Layer
2017
Journal of Low Power Electronics and Applications
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Due to their size, caches cannot store all of the code and data of an executing program. The cache memory is situated between the processor and the main memory Dynamic RAM (DRAM). ...
A cache is FA if a memory block can be mapped to any of its entries. FA permits any line in the main memory to be stored at any location in the cache. ...
hierarchy: the private L1 cache and public L2 cache. ...
doi:10.3390/jlpea7020014
fatcat:qgf4zaqltfcgpcd525wuio5dwq
ExplFrame: Exploiting Page Frame Cache for Fault Analysis of Block Ciphers
[article]
2020
arXiv
pre-print
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In this paper, we show that the page frame cache can be maliciously exploited by an adversary to steer the pages of a victim process to some pre-decided attacker-chosen locations in the memory. ...
Page Frame Cache (PFC) is a purely software cache, present in modern Linux based operating systems (OS), which stores the page frames that are recently being released by the processes running on a particular ...
The efficiency of this OS subsystem is mainly attributed to its intelligent usage of caching, which helps in taking advantage of the locality of reference (temporal and spacial) in the memory hierarchy ...
arXiv:1905.12974v3
fatcat:75mndajqtnau3karferdskatry
A case for exploiting subarray-level parallelism (SALP) in DRAM
2012
SIGARCH Computer Architecture News
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Modern DRAMs have multiple banks to serve multiple memory requests in parallel. ...
Our schemes also interact positively with applicationaware memory request scheduling in multi-core systems. ...
This research was also partially supported by grants from NSF (CAREER Award CCF-0953246), GSRC, and Intel ARO Memory Hierarchy Program. ...
doi:10.1145/2366231.2337202
fatcat:hhqburj7ync2bftmzo5yponp44
A case for exploiting subarray-level parallelism (SALP) in DRAM
2012
2012 39th Annual International Symposium on Computer Architecture (ISCA)
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Modern DRAMs have multiple banks to serve multiple memory requests in parallel. ...
Our schemes also interact positively with applicationaware memory request scheduling in multi-core systems. ...
This research was also partially supported by grants from NSF (CAREER Award CCF-0953246), GSRC, and Intel ARO Memory Hierarchy Program. ...
doi:10.1109/isca.2012.6237032
dblp:conf/isca/KimSLLM12
fatcat:gprplzdfhnfhtawazdb7pww5ta
Chisel
2014
SIGPLAN notices
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Emerging approximate hardware platforms provide approximate operations that, in return for reduced energy consumption and/or increased performance, exhibit reduced reliability and/or accuracy. ...
This research was supported in part by NSF (Grants CCF-1036241, CCF-1138967, and IIS-0835652), DOE (Grant DE-SC0008923), and DARPA (Grants FA8650-11-C-7192, FA8750-12-2-0110, and FA-8750-14-2-0004). ...
The value n in a faulty transition records the value that the fault inserted into the semantics of the program. ...
doi:10.1145/2714064.2660231
fatcat:a27g5ske3jcdxg7lc4bhxfew24
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