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Dynamic Power-Performance Adaptation of Parallel Computation on Chip Multiprocessors

Jian Li, J.F. Martinez
The Twelfth International Symposium on High-Performance Computer Architecture, 2006.  
Previous proposals for power-aware thread-level parallelism on chip multiprocessors (CMPs) mostly focus on multiprogrammed workloads.  ...  This work addresses the problem of dynamically optimizing power consumption of a parallel application that executes on a many-core CMP under a given performance constraint.  ...  INTRODUCTION Chip multiprocessors (CMPs) have emerged as a promising way to deliver sustained performance growth while relying less on raw circuit speed, and thus power [1] .  ... 
doi:10.1109/hpca.2006.1598114 dblp:conf/hpca/LiM06 fatcat:6hnet6w3wbhnvgo3ghzvl7uy3a

Optimizing array-intensive applications for on-chip multiprocessors

I. Kadayif, M. Kandemir, G. Chen, O. Ozturk, M. Karakoy, U. Sezer
2005 IEEE Transactions on Parallel and Distributed Systems  
Index Terms-On-chip multiprocessor, constrained optimization, embedded systems, energy consumption, adaptive loop parallelization, integer linear programming. ae 396  ...  In this paper, we focus on an on-chip multiprocessor architecture and present a set of code optimization strategies.  ...  Parts of this material were presented at DAC '02 (Design Automation Conference) [23] .  ... 
doi:10.1109/tpds.2005.57 fatcat:3qkvh55cozflrj2cgcm5miwqxa

Study of Various Factors Affecting Performance of Multi-Core Processors

Nitin Chaturvedi, Gurunarayanan S
2013 International Journal of Distributed and Parallel systems  
As Chip Multiprocessor system (CMP) become the predominant topology for leading microprocessors, critical components of the system are now integrated on a single chip.  ...  64 to 2048 entries on a 4 node, 8 node 16 node and 64 node Chip multiprocessor which in turn presents an open area of research on multicore processors with private/shared last level cache as the future  ...  Further performance gap between processors and memory require adaptive novel techniques to manage on chip cache memory judiciously. Figure2. Single Chip Multiprocessor (CMP)  ... 
doi:10.5121/ijdps.2013.4404 fatcat:ipcaejvdybaipejw5ehavdham4

A Taxonomy of Reconfigurable Single-/Multiprocessor Systems-on-Chip

Diana Göhringer, Thomas Perschke, Michael Hübner, Jürgen Becker
2009 International Journal of Reconfigurable Computing  
on the performance of an application.  ...  A simple example is the domain of high-performance computing applications found in meteorology or high-energy physics, where vector processors are the optimal choice.  ...  Introduction The usage of Multiprocessor System-on-Chip (MPSoC) for accelerating performance intensive applications is an upcoming trend in current chip technology.  ... 
doi:10.1155/2009/395018 fatcat:y5j3rgn7ejdojmjq7wfv26bymu

Energy-aware computation duplication for improving reliability in embedded chip multiprocessors

G. Chen, M. Kandemir, F. Li
2006 Proceedings of the 2006 conference on Asia South Pacific design automation - ASP-DAC '06  
Our experimental results indicate that the "percentage of duplicated computations" is a useful high-level metric for studying the tradeoffs among performance, power, and reliability.  ...  Focusing on an embedded chip multiprocessor and array-intensive applications, this paper demonstrates how reliability against transient errors can be improved without impacting execution time by utilizing  ...  We focus on execution of array-intensive applications on this chip multiprocessor.  ... 
doi:10.1145/1118299.1118342 fatcat:b46sxsjd4ngynanul3gzsmgevi

An adaptive chip-multiprocessor architecture for future mobile terminals

Mladen Nikitovic, Mats Brorsson
2002 Proceedings of the international conference on Compilers, architecture, and synthesis for embedded systems - CASES '02  
With several processors on one chip we can build a chip-multiprocessor (CMP) that can easily scale performance efficiently.  ...  We propose an adaptive chip-multiprocessor (CMP) architecture, where the number of active processors is dynamically adjusted to the current workload need in order to save energy while preserving performance  ...  We have in this study used a simulation based algorithm to decide when processors should go to a power-saving state. In reality, the decision should, of course, be taken by the operating system.  ... 
doi:10.1145/581636.581638 fatcat:pplg744ocnhtvizu32iab6jgp4

An adaptive chip-multiprocessor architecture for future mobile terminals

Mladen Nikitovic, Mats Brorsson
2002 Proceedings of the international conference on Compilers, architecture, and synthesis for embedded systems - CASES '02  
With several processors on one chip we can build a chip-multiprocessor (CMP) that can easily scale performance efficiently.  ...  We propose an adaptive chip-multiprocessor (CMP) architecture, where the number of active processors is dynamically adjusted to the current workload need in order to save energy while preserving performance  ...  We have in this study used a simulation based algorithm to decide when processors should go to a power-saving state. In reality, the decision should, of course, be taken by the operating system.  ... 
doi:10.1145/581630.581638 dblp:conf/cases/NikitovicB02 fatcat:3ss63yhaezb5hl5xbswruld4pm

Exploring Multiprocessor Design and Implementation Issues with In-Class Demonstrations

Naraig Manjikian
2010 Proceedings of the Canadian Engineering Education Association (CEEA)  
multiprocessor implemented in a programmable logic chip, and the use of parallel ray-tracing software to visualize speedup and load balance on a multicore desktop computer.  ...  The demonstrations include visualization of cache coherence behavior, remote login to a multiprocessor server to demonstrate parallel program execution, observation of internal behavior of a single-chip  ...  The demonstrations have included simulated execution of parallel programs for dynamic graphical visualization of multiprocessor cache coherence, on-line experimentation through remote login to measure  ... 
doi:10.24908/pceea.v0i0.3110 fatcat:gvfebmvkrfgojmg26alsxq7y34

Energy-efficient high-performance parallel and distributed computing

Samee Ullah Khan, Pascal Bouvry, Thomas Engel
2010 Journal of Supercomputing  
Acknowledgements The guest editors are in debt and give thanks to the knowledgeable reviewers that delivered timely assessments on the research articles submitted to this special issue.  ...  "Energy Efficient Scheduling of Parallel Tasks on Multiprocessor Computers" proposes a methodology to schedule parallel tasks on multiprocessors using dynamic voltage and speed scaling.  ...  "Reliability-Aware Platform Optimization for 3D Chip Multiprocessors" proposes an optimization methodology that integrates power, performance, and temperature for multiprocessor systems.  ... 
doi:10.1007/s11227-010-0485-0 fatcat:btx324wlwjgsvhybpac4tkp4ri

Power deregulation

Seunghoon Kim, Robert P. Dick, Russ Joseph
2007 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis - CODES+ISSS '07  
This method makes use of power gating, frequency scaling, and thread migration in chip-level multiprocessors to dynamically adjust to varying battery voltage.  ...  We have evaluated the power consumption, performance, and reliability implications of the proposed method using analytical techniques, power models, and detailed full-system simulation of numerous benchmarks  ...  This is the first work to propose using dynamic chip multiprocessor (CMP) core activation and frequency scaling to adapt to voltage reduction during battery use.  ... 
doi:10.1145/1289816.1289844 dblp:conf/codes/KimDJ07 fatcat:cxpylfwgizheve5bx6ijzqpddi

Boosting Parallel Applications Performance on Applying DIM Technique in a Multiprocessing Environment

Mateus B. Rutzig, Antonio C. S. Beck, Felipe Madruga, Marco A. Alves, Henrique C. Freitas, Nicolas Maillard, Philippe O. A. Navaux, Luigi Carro
2011 International Journal of Reconfigurable Computing  
We have successfully coupled a dynamic reconfigurable system to an SPARC-based multiprocessor and obtained performance gains of up to 40%, even for applications that show a great level of parallelism at  ...  Limits of instruction-level parallelism and higher transistor density sustain the increasing need for multiprocessor systems: they are rapidly taking over both general-purpose and embedded processor domains  ...  High-End Single Processor versus Homogeneous Multiprocessor Chip. Based on the above reasoning, one can compare the performance of the high-end single processor to the multiprocessor environment.  ... 
doi:10.1155/2011/546962 fatcat:rxidkhq36vgdthe4jvqvsrtq6y

Exploiting the Task-Pipelined Parallelism of Stream Programs on Many-Core GPUs

Shuai MU, Dongdong LI, Yubei CHEN, Yangdong DENG, Zhihua WANG
2013 IEICE transactions on information and systems  
In this paper, we focus on microarchitectural enhancements to enable task-pipelined execution of data-parallel kernels on GPUs.  ...  We propose an efficient adaptive dynamic scheduling mechanism and a moderately modified L2 design.  ...  By offering unprecedented processing power (e.g., 4300GFLOPS by AMD's Radeon HD7900 GPU [2] ) on a single chip, GPUs are dramatically changing the landscape of modern computing.  ... 
doi:10.1587/transinf.e96.d.2194 fatcat:ajkjy5a5vrbp5k3sxpqua66hpe

Scalable and Flexible heterogeneous multi-core system

Rashmi, Dr. Dinesh
2012 International Journal of Advanced Computer Science and Applications  
Keywords-Flexible Heterogeneous Multi Core system (FMC); instruction level parallelism, thread-level parallelism; and memorylevel parallelism; scalable; chip multiprocessors (CMP).  ...  Multi-core system has wide utility in today's applications due to less power consumption and high performance.  ...  B).TLP (Thread level parallelism) -It is a form of parallelization of computer code across multiple processors in parallel computing. c).  ... 
doi:10.14569/ijacsa.2012.031227 fatcat:m4vqub3x2fc7jlwm7dsb47ngzy

A fuzzy logic based dynamic reconfiguration scheme for optimal energy and throughput in symmetric chip multiprocessors

Muhammad Yasir Qadri, Klaus D. McDonald-Maier
2010 2010 NASA/ESA Conference on Adaptive Hardware and Systems  
The architecture incorporates reconfigurable level 1 (L1) caches, power gated cores and adaptive on-chip network routers to allow minimizing leakage energy effects for inactive components.  ...  This paper presents a novel coarse-grained reconfigurable symmetric chip multiprocessor (SCMP) architecture managed by a fuzzy logic engine that balances performance and energy consumption.  ...  The NAS parallel benchmarks are based on classical Computational Fluid Dynamics (CFD) applications.  ... 
doi:10.1109/ahs.2010.5546239 dblp:conf/ahs/QadriM10 fatcat:jba6t5io2bcqjig2lgdpg5xcda

Dynamic power management for UML modeled applications on multiprocessor SoC

Petri Kukkala, Tero Arpinen, Mikko Setälä, Marko Hännikäinen, Timo D. Hämäläinen, Reiner Creutzburg, Jarmo Takala, Jianfei Cai
2007 Multimedia on Mobile Devices 2007  
The paper presents a novel scheme of dynamic power management for UML modeled applications that are executed on a multiprocessor System-on-Chip (SoC) in a distributed manner.  ...  Application processes are considered as elementary units of distributed execution, and their mapping on a multiprocessor SoC can be dynamically changed at run-time.  ...  Further, the execution of a given application has to adapt to the varying resources, which can be performed at design and compilation time (static) as well as at runtime (dynamic). 3 Using the dynamic  ... 
doi:10.1117/12.707328 fatcat:xmqthhvtjbclzblrw46grrhqty
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