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Dynamic voltage scaling for commercial FPGAs

C.T. Chow, L.S.M. Tsui, P.H.W. Leong, W. Luk, S.J.E. Wilton
Proceedings. 2005 IEEE International Conference on Field-Programmable Technology, 2005.  
A methodology for supporting dynamic voltage scaling (DVS) on commercial FPGAs is described.  ...  applied to the FPGA.  ...  This paper introduces a new methodology to support dynamic voltage scaling (DVS) on commercial FPGAs.  ... 
doi:10.1109/fpt.2005.1568543 fatcat:zbd6vhqrwfdidmbdyrqhvvxoeu

Energy proportional computing in commercial FPGAs with adaptive voltage scaling

Jose Nunez-Yanez
2013 Proceedings of the 10th FPGAworld Conference on - FPGAworld '13  
This paper explores the capabilities of commercial FPGAs to use closed-loop adaptive voltage scaling to improve their energy and performance profiles beyond nominal.  ...  The results of deploying AVS in FPGAs shows power and energy savings exceeding 85% compared with nominal voltage operation at the same frequency or 100% better performance at nominal energy.  ...  A dynamic voltage scaling strategy for commercial FPGAs that aims to minimise power consumption for a giving task is presented in their work.  ... 
doi:10.1145/2513683.2513689 fatcat:ozo3u2rnq5ct5o77fcttvw2gji

Run-time power and performance scaling with CPU-FPGA hybrids

Jose Nunez-Yanez, Arash Beldachi
2014 2014 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)  
This paper investigates how a wide dynamic range of performance and power levels can be obtained in commercially available state-of-the-art hybrid FPGAs that include embedded processors.  ...  Adaptive voltage and frequency scaling obtained with embedded in-situ detectors is employed to scale performance and power in the FPGA fabric under processor control.  ...  A dynamic voltage scaling strategy for commercial FPGAs that aims to minimise power consumption for a giving task is presented in their work.  ... 
doi:10.1109/ahs.2014.6880158 dblp:conf/ahs/Nunez-YanezB14 fatcat:jqbbyaevqrbofc6ovenbg5giyu

Run-time power and performance scaling in 28 nm FPGAs

Arash Farhadi Beldachi, Jose L. Nunez-Yanez
2014 IET Computers & Digital Techniques  
Adaptive voltage and frequency scaling is employed to deliver proportional performance and power in these FPGA devices.  ...  In this context this paper investigates how these levels can be obtained in commercially available state-of-the-art 28 nm FPGAs and characterizes its benefits.  ...  A dynamic voltage scaling strategy for commercial FPGAs that aims to minimise power consumption for a giving task is presented in their work.  ... 
doi:10.1049/iet-cdt.2013.0117 fatcat:rf4g2eu2mzh2plwidaqcvimcmq

Adaptive Voltage Scaling with In-Situ Detectors in Commercial FPGAs

Jose Luis Nunez-Yanez
2015 IEEE transactions on computers  
A dynamic voltage scaling strategy for commercial FPGAs that aims to minimise power consumption for a giving task is presented in their work.  ...  We present a power adaptive architecture based on in-situ detectors and adaptive voltage scaling suitable for commercially available FPGAs. 2.  ... 
doi:10.1109/tc.2014.2365963 fatcat:fpbjprqw3rgb3nkcj53zs37cy4

Energy Optimization in Commercial FPGAs with Voltage, Frequency and Logic Scaling

Jose Luis Nunez-Yanez, Mohammad Hosseinabady, Arash Beldachi
2016 IEEE transactions on computers  
Run-time dynamic voltage scaling strategy for commercial FPGAs that aims to minimise power consumption for a giving task is presented in [14] .  ...  Section 2 Energy Optimization in Commercial FPGAs with Voltage, Frequency and Logic Scaling describes related work.  ... 
doi:10.1109/tc.2015.2435771 fatcat:ydgsir3i3bbvtibbbiamdrica4

Energy Efficient ALU Design Based On Voltage Scaling

2016 Gyancity Journal of Electronics and Computer Science  
In this paper we have designed Energy efficient ALU and calculated total power consumption of ALU by applying frequency and voltage scaling technique.  ...  We have done our Total Power Analysis of ALU on Spartan-3e FPGA.  ...  Voltage scaling has proven itself for energy efficient design of flip-flop too [4] . Voltage scaling is also related to soft error rate in SRAM Based FPGAs [5] .  ... 
doi:10.21058/gjecs.2016.11006 fatcat:vsfr3yetjzdrzh3y4ah2ogv3su

Scaling of Supply Voltage in Design of Energy Saver FIR Filter on 28nm FPGA

Bishwajeet Pandey, Vishal Jain, Rashmi Sharma, Mragang Yadav, D M Akbar Hussain
2017 International Journal of Control and Automation  
We have also taken three different level of voltage with 16 IO standards and we get three different power analysis for each IO Standards.  ...  of our FIR design using Verilog during implementation on 28nm FPGA.  ...  Voltage scaling is also used in FPGA based design of cyclic redundancy check [6] , flip-flop [7] and Wi-Fi Ah Channel enable ALU [8] . [9] Investigates the possibility of reductions possible in commercially  ... 
doi:10.14257/ijca.2017.10.12.07 fatcat:yc6ekgplszhjzozjjr7lzpux6m

High Performance FIFO Design for Processor through Voltage Scaling Technique

Abhay Saxena, Ashutosh Bhatt, Parth Gautam, Puneet Verma, Chandrashekhar Patel
2016 Indian Journal of Science and Technology  
Methods/Statistical Analysis: To make FPGA based design of FIFO we used voltages and frequency scaling techniques.  ...  Findings: The power consumption is reduced to 95.79% on voltage scaling where as there is a 4.38% less power consumption on frequency scaling.  ...  Related Work Adaptive voltage scaling with in-situ detectors in commercial FPGAs 1 . Energy Efficient Counter Design Using Voltage Scaling On FPGA 2 .  ... 
doi:10.17485/ijst/2016/v9i46/106916 fatcat:opv4oc6olbdorlevqvf2t5u7cu

Towards Power Efficient DNN Accelerator Design on Reconfigurable Platform [article]

Rourab Paul, Sreetama Sarkar, Suman Sau, Koushik Chakraborty, Sanghamitra Roy, Amlan Chakrabarti
2022 arXiv   pre-print
The simulation results substantiate the implementation of voltage scaled TPU in FPGAs and also justifies its power efficiency.  ...  Voltage scaling, a popular approach towards energy savings, can be a bit critical in FPGA as it may cause timing failure if not done in an appropriate way.  ...  VTR Environment In a commercial CAD environment biasing voltage is fixed.  ... 
arXiv:2102.06888v2 fatcat:qdhrna543ngpjdc2wifqfb5zam

Realizing a robust, reconfigurable active quenching design for multiple architectures of single-photon avalanche detectors [article]

Subash Sachidananda, Prithvi Gundlapalli, Victor Leong, Leonid Krivitsky, Alexander Ling
2022 arXiv   pre-print
We also demonstrate versatility of the circuit by directly testing custom fabricated chip-scale APDs, which paves the way for automated wafer-scale testing and characterization.  ...  Most active quench circuits used for single-photon avalanche detectors are designed either with discrete components which lack the flexibility of dynamically changing the control parameters, or with custom  ...  quench system with a widely used commercial APD (SAP500-T8), we further use it for testing our custom fabricated chip-scale APDs 15 in Geiger mode.  ... 
arXiv:2205.00228v1 fatcat:56fbbumid5h7nlphfroieo2j6i

Low-Power Warp Processor for Power Efficient High-Performance Embedded Systems

Roman Lysecky
2007 2007 Design, Automation & Test in Europe Conference & Exhibition  
custom hardware circuits in an on-chip FPGA.  ...  We further demonstrate the flexibility of this approach to provide dynamic control between high-performance and low-power consumption.  ...  The low-power architecture will take advantage of the voltage and frequency scaling capabilities of the XScale processor and incorporate dynamic clock management to support frequency scaling for the on-chip  ... 
doi:10.1109/date.2007.364581 dblp:conf/date/Lysecky07 fatcat:govqp3yxzzgjzilhxz53iio7vu

FPGA Energy Efficiency by Leveraging Thermal Margin [article]

Behnam Khaleghi, Sahand Salamat, Mohsen Imani, Tajana Rosing
2019 arXiv   pre-print
There are hurdles for such opportunistic voltage scaling in FPGAs because (a) critical paths change with designs, making timing evaluation difficult as voltage changes, (b) each FPGA resource has particular  ...  By comprehensively analyzing the timing and power consumption of FPGA building blocks under varying temperatures and voltages, we propose a thermal-aware voltage scaling flow that effectively utilizes  ...  Fig. 5 . 5 The proposed simulation flow for FPGA-mapped applications, enabling speculative voltage scaling.  ... 
arXiv:1911.07187v1 fatcat:bpepxd6e6jhlpied3h2rcyv25e

An Overview of Low-Power Techniques for Field-Programmable Gate Arrays

Julien Lamoureux, Wayne Luk
2008 2008 NASA/ESA Conference on Adaptive Hardware and Systems  
This paper provides an overview of low-power techniques for field-programmable gate arrays (FPGAs ).  ...  It covers system-level design techniques and device-level design techniques that have targeted current commercial devices.  ...  (e) Dynamic voltage scaling can be used to adapt the supply voltage to the FPGA as the temperature changes, to minimise power consumption.  ... 
doi:10.1109/ahs.2008.71 dblp:conf/ahs/LamoureuxL08 fatcat:xdtvjfckenduxosf5tpoj3v4kq

Voltage Scalling Based Traffic Light Controller Design on Virtex-7 FPGA Family

Sujeet Pandey, Bhagwan Das, D M A Hussain
2018 Gyancity Journal of Engineering and Technology  
, 75.59% and 86.96% in leakage power as the voltage is scale down from 1.8V to 1.6V, 1.4V and 1.2V respectively at ambient temperature 50 o C.  ...  There is a reduction of 46.31%, 70.11% and 82.58% in clock power as the voltage is scale down from 1.8V to 1.6V, 1.4V and 1.2V respectively at any value of ambient temperature.  ...  Some other researcher has work on Adaptive voltage scaling with in-situ detectors in commercial FPGAs [2] .  ... 
doi:10.21058/gjet.2018.41004 fatcat:nt6sd3g37bd75hmebcrqb5e2ky
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