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High-Performance Embedded Architecture and Compilation Roadmap [chapter]

Koen De Bosschere, Wayne Luk, Xavier Martorell, Nacho Navarro, Mike O'Boyle, Dionisios Pnevmatikatos, Alex Ramirez, Pascal Sainrat, André Seznec, Per Stenström, Olivier Temam
2007 Lecture Notes in Computer Science  
One of the key deliverables of the EU HiPEAC FP6 Network of Excellence is a roadmap on high-performance embedded architecture and compilation -the HiPEAC Roadmap for short.  ...  (vi) runtime systems, (vii) benchmarking, (viii) simulation and system modeling, (ix) reconfigurable computing, and (x) real-time systems.  ...  network-on-chip (NoC) technologies.  ... 
doi:10.1007/978-3-540-71528-3_2 fatcat:ywmebvj7wrfb3ojghsjs4w3fy4

Guest Editorial: IEEE TC Special Issue On Communications for Many-core Processors and Accelerators

Zhonghai Lu
2021 IEEE transactions on computers  
Meanwhile, data-intensive workloads pose greater challenges to both on-chip and off-chip communications, whereas emerging technologies offer new opportunities for interconnection networks.  ...  Optical link candidates are dynamically chosen to maximize traffic offloading revenue and then selected for adaptive routing based on flexible objectives.  ...  based on a graph topology well-suited for convolutional neural networks (CNNs).  ... 
doi:10.1109/tc.2021.3068060 fatcat:pcxs27wbr5h3riejjuzfgdtbqm

Performance Evaluation of Application Mapping Approaches for Network-on-Chip Designs

Waqar Amin, Fawad Hussain, Sheraz Anjum, Sarzamin Khan, Naveed Khan Baloch, Zulqar Nain, Sung Won Kim
2020 IEEE Access  
Network-on-chip (NoC) is evolving as a better substitute for incorporating a large number of cores on a single system-on-chip (SoC).  ...  Moreover, the best technique identified in each category based on the evaluation of performance results. INDEX TERMS Network-on-Chip, application mapping, NoC design, VOPD, System-on-Chip.  ...  In [42] , a dynamic task mapping with a congestion speculation (DTMCS) technique has been discussed.  ... 
doi:10.1109/access.2020.2982675 fatcat:kn6mkit3uvguvc2w6lx5dgddoe

Cardio: Adaptive CMPs for reliability through dynamic introspective operation

Andrea Pellegrini, Valeria Bertacco
2011 2011 IEEE International High Level Design Validation and Test Workshop  
We estimate its dynamic reconfiguration time to be comprised between 20 and 50 thousand cycles per failure. Hardware  ...  In this work, we propose Cardio, a distributed architecture for reliable chip multiprocessors.  ...  For our on-chip dynamic discovery system, we decided to adopt a routing algorithm inspired by link-state.  ... 
doi:10.1109/hldvt.2011.6113983 dblp:conf/hldvt/PellegriniB11 fatcat:tshn2j45prc3hpovyuvrbcbihm

Cardio: CMP Adaptation for Reliability Through Dynamic Introspective Operation

Andrea Pellegrini, Valeria Bertacco
2014 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
With the goal of addressing this issue, we propose Cardio: a low-cost architecture for reliable chip multiprocessors.  ...  Our experimental evaluation indicates that the overall performance impact of Cardio is as low as 4.5%, and its dynamic reconfiguration time upon fault detection is comprised between 20 and 50 thousand  ...  Resource managers use the information about local connections broadcasted by the routers to generate a connectivity map of the on-chip network.  ... 
doi:10.1109/tcad.2013.2284008 fatcat:hvzlyhcjzvhhlir3zfsvfbq63a

NOC'S: Buffered and Bufferless Structure and their design methodologies for High throughput and Low latency

Sujata. S.B
2020 International Journal of Advanced Trends in Computer Science and Engineering  
To know and meet the existing issues and demands related to scalability of number of nodes, their sizes of Network on Chip (NoC) which are important networks for efficient communication to transfer multimedia  ...  At the last, modified buffered and bufferless NoC architectures are proposed which includes the modified routing algorithm called Dynamically buffered and bufferless reconfigurable NoC (DB 2 R-NoC's) and  ...  Since System-on-Chip (SoC) is usually battery-powered the Network-on-Chip (NoC) becomes one of the important tasks for energy proficiency and its communication subdivision.  ... 
doi:10.30534/ijatcse/2020/240932020 fatcat:kj4yllfklffqrjuaipr2c26jyy

Supporting non-contiguous processor allocation in mesh-based CMPs using virtual point-to-point links

M Asadinia, M Modarressi, A Tavakkol, H Sarbazi-Azad
2011 2011 Design, Automation & Test in Europe  
In this paper, we propose a processor allocation mechanism for run-time assignment of a set of communicating tasks of input applications onto the processing nodes of a Chip Multiprocessor (CMP), when the  ...  This mechanism targets the on-chip communication and aims to reduce the power and latency of the NoC employed as the communication infrastructure.  ...  INTRODUCTION In networks-on-chip (NoCs), the problem of task to node mapping, which determines on which node (or respective processing core) each task should be placed at, dramatically affects network  ... 
doi:10.1109/date.2011.5763072 dblp:conf/date/AsadiniaMTS11 fatcat:sexhjoibe5evfavim6x67fmvfa

Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives

Radu Marculescu, Umit Y. Ogras, Li-Shiuan Peh, Natalie Enright Jerger, Yatin Hoskote
2009 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
Index Terms-Energy and power consumption, multiprocessor systems-on-chip (MPSoCs), networks-on-chip (NoCs), on-chip communication.  ...  To alleviate the complex communication problems that arise as the number of on-chip components increases, network-on-chip (NoC) architectures have been recently proposed to replace global interconnects  ...  Marculescu of Carnegie Mellon University for the valuable feedback in the early stages of the manuscript.  ... 
doi:10.1109/tcad.2008.2010691 fatcat:2doy6ne6ybeptgy2avgvzjloji

The pressure is on [computer systems research]

K. Kavi, J.C. Browne, A. Tripathi
1999 Computer  
Because many processing elements reside on the same chip, communication among tasks is very efficient.  ...  Current WANs do not deal with congestion effectively, offer poor support for quality of service (QoS), and have low reliability.  ... 
doi:10.1109/2.738301 fatcat:37juh2i5yjhxtdajris5w5ewvq

The future of electronics based on memristive systems

Mohammed A. Zidan, John Paul Strachan, Wei D. Lu
2018 Nature Electronics  
We highlight three areas of potential technological impact: on-chip memory and storage, biologically inspired computing and general-purpose in-memory computing.  ...  in terms of obtaining fundamental control of the atomic-level dynamics.  ...  Acknowledgements We acknowledge inspiring discussions with R. S. Williams, G. Astfalk, X. Zhu, W. Ma, F. Cai and Y. Jeong. This work was supported in part by the National Science Foundation  ... 
doi:10.1038/s41928-017-0006-8 fatcat:4olytq7gkjctthfuzq5ivnl2ou

Tartan

Mahim Mishra, Timothy J. Callahan, Tiberiu Chelcea, Girish Venkataramani, Seth C. Goldstein, Mihai Budiu
2006 SIGPLAN notices  
To this end, we evaluate the performance and energy efficiency of entire applications on Tartan, a general-purpose architecture which integrates a reconfigurable fabric (RF) with a superscalar core.  ...  The interconnect uses static configuration and routing at the lower levels and a packet-switched, dynamically-routed network at the top level.  ...  The authors would like to thank David Koes, Mukesh Agrawal, David Andersen and the anonymous reviewers for many helpful comments and suggestions.  ... 
doi:10.1145/1168918.1168878 fatcat:ucz7r3b7l5fkrdr722oh5smup4

Tartan

Mahim Mishra, Timothy J. Callahan, Tiberiu Chelcea, Girish Venkataramani, Seth C. Goldstein, Mihai Budiu
2006 Proceedings of the 12th international conference on Architectural support for programming languages and operating systems - ASPLOS-XII  
To this end, we evaluate the performance and energy efficiency of entire applications on Tartan, a general-purpose architecture which integrates a reconfigurable fabric (RF) with a superscalar core.  ...  The interconnect uses static configuration and routing at the lower levels and a packet-switched, dynamically-routed network at the top level.  ...  The authors would like to thank David Koes, Mukesh Agrawal, David Andersen and the anonymous reviewers for many helpful comments and suggestions.  ... 
doi:10.1145/1168857.1168878 dblp:conf/asplos/MishraCCVGB06 fatcat:wrasrawnezceho6oxl4h3jdogq

Tartan

Mahim Mishra, Timothy J. Callahan, Tiberiu Chelcea, Girish Venkataramani, Seth C. Goldstein, Mihai Budiu
2006 SIGARCH Computer Architecture News  
To this end, we evaluate the performance and energy efficiency of entire applications on Tartan, a general-purpose architecture which integrates a reconfigurable fabric (RF) with a superscalar core.  ...  The interconnect uses static configuration and routing at the lower levels and a packet-switched, dynamically-routed network at the top level.  ...  The authors would like to thank David Koes, Mukesh Agrawal, David Andersen and the anonymous reviewers for many helpful comments and suggestions.  ... 
doi:10.1145/1168919.1168878 fatcat:j4x64jtkk5c3xbiq5wk7jmrrpq

Tartan

Mahim Mishra, Timothy J. Callahan, Tiberiu Chelcea, Girish Venkataramani, Seth C. Goldstein, Mihai Budiu
2006 ACM SIGOPS Operating Systems Review  
To this end, we evaluate the performance and energy efficiency of entire applications on Tartan, a general-purpose architecture which integrates a reconfigurable fabric (RF) with a superscalar core.  ...  The interconnect uses static configuration and routing at the lower levels and a packet-switched, dynamically-routed network at the top level.  ...  The authors would like to thank David Koes, Mukesh Agrawal, David Andersen and the anonymous reviewers for many helpful comments and suggestions.  ... 
doi:10.1145/1168917.1168878 fatcat:bob3swewongxxm565o3ddwprii

Towards simulator-like observability for FPGAs

Eddie Hung, Steven J.E. Wilton
2013 Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays - FPGA '13  
signals to all on-chip trace-buffers.  ...  Rather than connecting a predetermined subset of circuits signals to dedicated trace-buffer inputs at compile-time, in this work we propose that a virtual overlay network is built to multiplex all on-chip  ...  Acknowledgements The authors are grateful to Altera for supporting this work, and would also like to acknowledge Wayne Luk and the Department of Computing at Imperial College London, where most of this  ... 
doi:10.1145/2435264.2435272 dblp:conf/fpga/HungW13 fatcat:pb3appshn5hilga3ssfgye434y
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