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A system on chip-based real-time tracking system for amphibious spherical robots

Shuxiang Guo, Shaowu Pan, Xiaoqiong Li, Liwei Shi, Pengyi Zhang, Ping Guo, Yanlin He
2017 International Journal of Advanced Robotic Systems  
Moreover, dynamic reconfiguration was used to switch accelerators online for reducing resource consumption and improving system adaptability.  ...  And customized image accelerators were deployed on the field programmable gate array subsystem to speed up the timeconsuming processes of visual algorithms.  ...  Declaration of conflicting interests The author(s) declared no potential conflicts of interest with respect to the research, authorship and/or publication of this article.  ... 
doi:10.1177/1729881417716559 fatcat:mezol6kpxrfkvcwb3jcwwnujqy

Improving Correctness of Logic Circuit using Self-Healing Built-In Logic Test Module in FPGA using Dynamic Partial Reconfiguration

2019 International journal of recent technology and engineering  
In the proposed work, Advanced Encryption Standard (AES) circuit parts are checked for correctness by using in-built Secure Hash Algorithm (SHA) and corrected by Dynamic Partial Reconfiguration (DPR).  ...  Because of the reconfiguration nature of FPGAs, it become a good choice rather than ASIC on cloud.  ...  Module in FPGA using Dynamic Partial Reconfiguration Manjith B.C. algorithm.  ... 
doi:10.35940/ijrte.b2104.078219 fatcat:oflnngnomfdytevg2a65jbybta

Dynamically reconfigurable systolic array accelerators: a case study with extended Kalman filter and discrete wavelet transform algorithms

A. Sudarsanam, A. Dasu, R. Kallam, J. Carver, R. Barnes
2010 IET Computers & Digital Techniques  
(iii) A hybrid partial dynamic iv reconfiguration method that combines Xilinx early access partial reconfiguration, on-chip bitstream decompression, and bitstream relocation to enable fast scaling of systolic  ...  (i) A polymorphic systolic array framework comprising of reconfigurable partial region-based sockets to accelerate algorithms amenable to being mapped onto linear systolic arrays.  ...  Partial Dynamic Reconfiguration Partial Dynamic Reconfiguration (PDR) [37] [38] [39] is the process of reconfiguring only a portion of an FPGA at run-time, after initial configuration, while the other  ... 
doi:10.1049/iet-cdt.2008.0139 fatcat:crmmlzzywrcyzhgijyqd2nzfci

Configuration relocation and defragmentation for run-time reconfigurable computing

K. Compton, Zhiyuan Li, J. Cooley, S. Knol, S. Hauck
2002 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
Due to its potential to greatly accelerate a wide variety of applications, reconfigurable computing has become a subject of a great deal of research.  ...  By mapping the compute-intensive sections of an application to reconfigurable hardware, custom computing systems exhibit significant speedups over traditional microprocessors.  ...  Using a single row offset and an adder provides a simple way to dynamically relocate individual configurations to fit available free space.  ... 
doi:10.1109/tvlsi.2002.1043324 fatcat:sa4tppuug5c6vbr5pzm5v2e2fi

A Soft Dual-Processor System with a Partially Run-Time Reconfigurable Shared 128-Bit SIMD Engine

Jose Raul Garcia Ordaz, Dirk Koch
2018 2018 IEEE 29th International Conference on Application-specific Systems, Architectures and Processors (ASAP)  
In this work, we present a soft dual-processor system that, as a distinctive feature, seamlessly integrates a partially run-time reconfigurable 128-bit SIMD engine.  ...  We show that the proposed SIMD engine increases performance-per-area and that it can be used to substantially accelerate time consuming kernels for a set of media applications.  ...  Correspondingly, the dynamic subsystem is implemented on top of a partially run-time reconfigurable (PRR) region in the FPGA, as described in Section IV. A.  ... 
doi:10.1109/asap.2018.8445115 dblp:conf/asap/OrdazK18 fatcat:gckiewwtdvbe5kpodi72jenjja

On-the-fly Composition of FPGA-Based SQL Query Accelerators Using a Partially Reconfigurable Module Library

Christopher Dennl, Daniel Ziener, Jurgen Teich
2012 2012 IEEE 20th International Symposium on Field-Programmable Custom Computing Machines  
In this paper, we introduce a novel FPGA-based methodology for accelerating SQL queries using dynamic partial reconfiguration.  ...  In our approach, an SQL query is transformed into a hardware pipeline consisting of partially reconfigurable modules.  ...  However, it is unaffordable to build one special accelerator for each possible query. Therefore, we make use of the possibility of partial reconfiguration.  ... 
doi:10.1109/fccm.2012.18 dblp:conf/fccm/DennlZT12 fatcat:lynqtturcfedpdzkok2qil6s7m

On implementability of Polymorphic Register Files

Catalin Ciobanu, Georgi Kuzmanov, Georgi Gaydadjiev
2012 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)  
Our PRF implementation uses a 2D array of p × q linearly addressable memory banks, with customized addressing functions to avoid address routing circuits.  ...  We target one single-view and a set of four non redundant multi-view parallel memory schemes that cover all widely used access patterns in scientific and multimedia applications: 1) p × q rectangle, p  ...  Therefore, we will investigate the potential of employing custom solutions, or even dynamic runtime customization of the interconnect using partial reconfiguration.  ... 
doi:10.1109/recosoc.2012.6322873 dblp:conf/recosoc/CiobanuKG12 fatcat:qpw6e6phuzcfzbszu6ec5l7gna

Table of contents

2019 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
Redouté 103 Dynamic Partial Reconfiguration of Customized Single-Row Accelerators .................................................. ....................................................................  ...  Manohar 83 A High-Throughput Hardware Accelerator for Lossless Compression of a DDR4 Command Trace ..................... ................................................................................  ... 
doi:10.1109/tvlsi.2018.2889282 fatcat:rtkn3au4lbdvhgjxynyrtmnk74

A partially reconfigurable architecture supporting hardware threads

Ying Wang, Jian Yan, Xuegong Zhou, Lingli Wang, Wayne Luk, Chenglian Peng, Jiarong Tong
2012 2012 International Conference on Field-Programmable Technology  
As a promising computing platform for stream processing, partially reconfigurable systems have shown their hardware efficiency and reconfiguration flexibility.  ...  This paper presents a partially reconfigurable architecture supporting hardware threads. It gives a unified software/hardware thread interface and high throughput point-to-point streaming structure.  ...  The partially reconfigurable system is built on our custom board.  ... 
doi:10.1109/fpt.2012.6412147 dblp:conf/fpt/WangYZWLPT12 fatcat:niunijrbcjdclfdt4vqzigl7hm

FPGA Dynamic and Partial Reconfiguration

Kizheppatt Vipin, Suhaib A. Fahmy
2018 ACM Computing Surveys  
Dynamic and partial reconfiguration are key differentiating capabilities of field programmable gate arrays (FPGAs).  ...  We review FPGA reconfiguration, looking at architectures built for the purpose, and the properties of modern commercial architectures.  ...  PR can extend this approach to allow integration of custom hardware accelerators that can be dynamically changed at runtime.  ... 
doi:10.1145/3193827 fatcat:tbks3e734zdkdceihncpdeawia

Efficient, Dynamic Multi-task Execution on FPGA-based Computing Systems

Umar Minhas, Roger Woods, Dimitrios S. Nikolopoulos, Georgios Karakonstantis
2021 IEEE Transactions on Parallel and Distributed Systems  
This results in suboptimal resource utilisation and relatively poor performance, particularly as the number of tasks increase.  ...  Using OpenCL's exploration capabilities, we employ clever clustering and custom, task-specific partitioning and mapping to create a novel, area sharing methodology where task resource requirements are  ...  In total, there are 80 rows of the FPGA that can be configured as a single region or a set of two homogeneous regions of 40 rows each.  ... 
doi:10.1109/tpds.2021.3101153 fatcat:cpixjpmwx5dwpdgyhss5mxy6oq

Module relocation in Heterogeneous Reconfigurable Systems-on-Chip using the Xilinx Isolation Design Flow

L. Gantel, M.E.A Benkhelifa, F. Lemonnier, F. Verdier
2012 2012 International Conference on Reconfigurable Computing and FPGAs  
Combining techniques such as dynamic and partial reconfiguration and partial readback with the knowledge of the bitstream structure offer the ability to target several partitions using a unique configuration  ...  Heterogeneous Reconfigurable Systems-on-Chip (HRSoC) contain as their name suggests, heterogeneous processing elements in a single chip.  ...  INTRODUCTION With the flexibility brought by the Dynamic and Partial Reconfiguration (DPR), the adaptation of the thread model on the hardware accelerator became interesting.  ... 
doi:10.1109/reconfig.2012.6416763 dblp:conf/reconfig/GantelBLV12 fatcat:fqh4iftxefbfhf42og7i5sbxni

Modeling and exploration of a reconfigurable architecture for digital holographic imaging

Thomas Lenart, Henrik Svensson, Viktor Owall
2008 2008 IEEE International Symposium on Circuits and Systems  
The use of coarse-grain reconfigurable architectures (CGRA) is a suitable alternative for hardware acceleration in many application areas, including digital holographic imaging.  ...  We present our SystemC-based exploration environment (SCENIC) and methodology used to construct and evaluate systems containing reconfigurable architectures.  ...  The resource cells are configured with the functional unit specified in the tile description file, but can also be configured during simulation to support partial dynamic reconfiguration. 2) Topology generator  ... 
doi:10.1109/iscas.2008.4541401 dblp:conf/iscas/LenartSO08 fatcat:rolecz5eqbenlhajaiyugtgebq

Improving Reliability, Security, and Efficiency of Reconfigurable Hardware Systems [article]

Daniel Ziener
2018 arXiv   pre-print
transform static circuit structures into dynamic ones by applying dynamic partial reconfiguration.  ...  In this treatise, my research on methods to improve efficiency, reliability, and security of reconfigurable hardware systems, i.e., FPGAs, through partial dynamic reconfiguration is outlined.  ...  The research has been carried out in collaboration with several doctoral researchers, master and bachelor students from my research group Reconfigurable Computing. In  ... 
arXiv:1809.11156v1 fatcat:6ttulp2tancyvds7fk2coxoptq

A multiprocessor self-reconfigurable JPEG2000 encoder

Antonino Tumeo, Simone Borgio, Davide Bosisio, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto
2009 2009 IEEE International Symposium on Parallel & Distributed Processing  
While on a standard single processor architecture the partial dynamic reconfiguration requires the processor to stop working to instantiate the hardware threads, the proposed solution hides most of the  ...  Thanks to partial dynamic reconfiguration, this system can, at run time, spawn both software and hardware threads, sharing not only the general purpose soft-cores present in the architecture but also area  ...  , without considering partial dynamic reconfiguration.  ... 
doi:10.1109/ipdps.2009.5161198 dblp:conf/ipps/TumeoBBMPFS09 fatcat:wwtmucew6rggzaj5ckejliavba
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