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Dynamic Partial Order Reductions for Spinloops [article]

Michalis Kokologiannakis, Xiaowei Ren, Viktor Vafeiadis
2021
Stateless model checking (SMC) coupled with dynamic partial order reduction (DPOR) is an effective way for automatically verifying safety properties of loop-free concurrent programs.  ...  We present SAVER (Spinloop-Aware Verifier), a memorymodel- agnostic SMC/DPOR extension that detects zero-net-effect spinloops and avoids redundant explorations that lead to the same local state.  ...  ACKNOWLEDGMENTS This work was supported by a European Research Council (ERC) Consolidator Grant for the project "PERSIST" under the European Union's Horizon 2020 research and innovation programme (grant  ... 
doi:10.34727/2021/isbn.978-3-85448-046-4_25 fatcat:dm4jqbroyjhdvbj3wcjd66nyti

Dynamic verification of Multicore Communication applications in MCAPI

Subodh Sharma, Ganesh Gopalakrishnan, Eric Mercer
2009 2009 IEEE International High Level Design Validation and Test Workshop  
We present a dynamic direct code verification tool called MCC (MCAPI Checker) for applications written in the newly proposed Multicore Communications API (MCAPI).  ...  This is the first dynamic model checker for MCAPI applications, and as such our work provides designers the opportunity to use a formal design tool in verifying MCAPI applications and evaluating MCAPI  ...  Dynamic verification methods differ in the way in which the partial order reduction (POR) method operates within them.  ... 
doi:10.1109/hldvt.2009.5340169 dblp:conf/hldvt/SharmaGM09 fatcat:xoa5uxpc2vcrhhep4dxkfculw4

Awaiting for Godot: Stateless Model Checking that Avoids Executions where Nothing Happens [article]

Bengt Jonsson, Magnus Lång, Konstantinos Sagonas
2022 arXiv   pre-print
It is highly effective when coupled with Dynamic Partial Order Reduction (DPOR), which introduces an equivalence on schedulings and need explore only one in each equivalence class.  ...  Stateless Model Checking (SMC) is a verification technique for concurrent programs that checks for safety violations by exploring all possible thread schedulings.  ...  ACKNOWLEDGEMENTS This work was partially supported by the Swedish Research Council through grants #621-2017-04812 and 2019-05466, and by the Swedish Foundation for Strategic Research through project aSSIsT  ... 
arXiv:2208.09259v1 fatcat:kwh7gqnburf5zlzvahviepdt5y

Verifying Local Transformations on Relaxed Memory Models [chapter]

Sebastian Burckhardt, Madanlal Musuvathi, Vasu Singh
2010 Lecture Notes in Computer Science  
In this paper, we present a novel proof methodology for verifying that a local program transformation is sound with respect to a specific hardware memory model, in the sense that it is not observable in  ...  For concurrent shared-memory programs this task is challenging because (1) concurrent threads can observe transformations that would be undetectable in a sequential program, and (2) contemporary multiprocessors  ...  As expected, the first two transformations (load-reordering, store-reordering) are unsound for all models except models that specifically relax load-load order or store-store order.  ... 
doi:10.1007/978-3-642-11970-5_7 fatcat:6ilyx6uf7bcnnpq5ohdojqtity

Enabling Realistic Fine-Grain Voltage Scaling with Reconfigurable Power Distribution Networks

Waclaw Godycki, Christopher Torng, Ivan Bukreyev, Alyssa Apsel, Christopher Batten
2014 2014 47th Annual IEEE/ACM International Symposium on Microarchitecture  
In this paper, we use architecture-level modeling to explore a new dynamic voltage/frequency scaling controller called the fine-grain synchronization controller (FG-SYNC+).  ...  FG-SYNC+ enables improved performance and energy efficiency at similar average power for multithreaded applications with activity imbalance.  ...  The authors acknowledge and thank Ji Kim for his help in developing the instruction-based energy model, and Derek Lockhart, Shreesha Srinath, and Pol Rosello for their help in writing multicore application  ... 
doi:10.1109/micro.2014.52 dblp:conf/micro/GodyckiTBAB14 fatcat:biubyif6bnfjhl3lnkshuhrbhm

A dataflow-like programming model for future hybrid clusters

Jens Breitbart
2013 International Journal of Networking and Computing  
Broadcast, scatter and gather are modeled based on data distribution among the nodes, whereas reduction and scan follow a combining PRAM approach of having multiple threads write to the same memory location  ...  However, the techniques partially returned in, e. g., out of order architectures, although at a smaller scale than originally planned.  ...  MIC consists of multiple x86 based in-order CPUs with large vector units. We identified three major challenges crucial for a programming system for upcoming hybrid chips.  ... 
doi:10.15803/ijnc.3.1_15 fatcat:hzcymccayzfs7dt3t6ukkcg274

Inter-workgroup barrier synchronisation on graphics processing units

Tyler Sorensen, Alastair Donaldson, Intel Corporation
2019
create an execution environment that allows for a safe and portable global barrier across a subset of the GPU threads.  ...  thesis includes the following studies: Execution models: while a general global barrier can deadlock due to starvation on GPUs, it is shown that the scheduling guarantees of current GPUs can be used to dynamically  ...  The spinloops and intra-workgroup barriers constrain the execution such that there is essentially only one execution allowed.  ... 
doi:10.25560/68006 fatcat:6ogn37ahvnci3ooke5w42bxewu