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Dynamic Dictionary-Based Data Compression for Level-1 Caches
[chapter]
2006
Lecture Notes in Computer Science
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In this paper, we propose the first dynamic dictionary-based compression mechanism for L1 data caches. ...
Data cache compression is actively studied as a venue to make better use of onchip transistors, increase apparent capacity of caches, and hide the long memory latencies. ...
Conclusions In this paper, we propose the first mechanism -to best the of our knowledge-for dynamic dictionary-based compression for L1 data caches. ...
doi:10.1007/11682127_9
fatcat:pzq6jppbcbdzdftpsbtwwf7ofi
A VLSI Approach for Cache Compression in Microprocessor
2011
International Journal of Instrumentation Control and Automation
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Proposed hardware compression algorithms fall into the dictionary-based category, which depend on building a dictionary and using its entries to encode repeated data values. ...
Because of these, designers of memory system may find cache compression as an advantageous method to increase speed of a microprocessor based system, as it increases cache capacity and off-chip bandwidth ...
Cache compression is one such technique; data in last-level onchip caches, e.g., L2 resulting in larger usable caches. ...
doi:10.47893/ijica.2011.1034
fatcat:r4etyf4trndyndjkafbmwinnfi
A performance and energy exploration of dictionary code compression architectures
2011
2011 International Green Computing Conference and Workshops
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We have implemented and evaluated a novel dictionary code compression mechanism where frequently executed individual instructions and/or sequences are replaced in memory with short code words. ...
The result is a dramatically reduced instruction memory access frequency leading to a performance improvement for small instruction cache sizes and to significantly reduced energy consumption in the instruction ...
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doi:10.1109/igcc.2011.6008584
dblp:conf/green/CollinBO11
fatcat:uxa7t77chvfqfevgas3uzaxysi
Compression-aware dynamic cache reconfiguration for embedded systems
2012
Sustainable Computing: Informatics and Systems
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Dynamic cache reconfiguration is very effective to reduce energy consumption of cache subsystems which accounts for about half of the total energy consumption in embedded systems. ...
We developed efficient heuristics to explore large space of two-level cache hierarchy in order to study the effect of a two-level cache on energy consumption. ...
Fig. 4 illustrates an example of bitmask-based compression in which it can compress up to six data entries using bitmask-based compression, whereas using only dictionary-based compression would compress ...
doi:10.1016/j.suscom.2012.01.003
fatcat:o4hmgczzqrdjvlssoow7db5b2i
Understanding Cache Compression
2021
ACM Transactions on Architecture and Code Optimization (TACO)
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This study sheds light on the challenges of adopting compression in cache design—from the shrinking of the data until its physical placement. ...
It is expected that this article will ease the understanding of decisions to be taken for the design of compressed systems and provide directions for future work. ...
Example of full match (MM and XX) compression using: (1) local dynamic dictionaries (top A'B' pair, in red)lines are compressed isolatedly; (2) shared local dynamic dictionaries (middle, blue)-both lines ...
doi:10.1145/3457207
fatcat:2jsbv7d3qfd53kpyiv44cpcfne
C-Pack: A High-Performance Microprocessor Cache Compression Algorithm
2010
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
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In this work, we present a lossless compression algorithm that has been designed for fast on-line data compression, and cache compression in particular. ...
a single dictionary and without degradation in compression ratio. ...
Alameldeen at Intel Corporation for his help understanding his cache compression research results. ...
doi:10.1109/tvlsi.2009.2020989
fatcat:vl2hhmdxfzealpkjnd6z2a6z7e
Request Schedule Oriented Compression Cache Memory
2018
International Journal of Engineering & Technology
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Re-cent advancement paved way for compressing data in cache, accessing recent data use pat-tern etc. ...
So that cache searching and indexing speed gets reduced considerably and service the request in a faster manner. For capacity and replacement improvements Dictionary sharing based caching is used. ...
Dynamic Dictionary Based Compression The Dictionary can be made while storing the data in cache and may vary from one cache line to another. ...
doi:10.14419/ijet.v7i2.19.15053
fatcat:uphbredfcvdkrdsumfez64mmae
Synergistic integration of dynamic cache reconfiguration and code compression in embedded systems
2011
2011 International Green Computing Conference and Workshops
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Dynamic cache reconfiguration is very effective to reduce energy consumption of cache subsystems which accounts for about half of the total energy consumption in embedded systems. ...
In this paper, we study the challenges and associated opportunities in integrating dynamic cache reconfiguration with code compression to retain the advantages of both approaches. ...
Fig. 4 illustrates an example of bitmask-based compression in which it can compress up to six data entries using bitmask-based compression, whereas using only dictionary-based compression would compress ...
doi:10.1109/igcc.2011.6008580
dblp:conf/green/HajimiriRM11
fatcat:wx6kniipava5fab346qw7iwrg4
C-Pack: Cache Compression for Microprocessor Performance
2011
International Journal of Power System Operation and Energy Management
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In this work, I present a lossless compression algorithm that has been designed for fast on-line data compression, and cache compression in particular. ...
a single dictionary and without degradation in compression ratio. ...
C-Pack achieves compression by two means: (1) it uses statically decided, compact encodings for frequently appearing data words and (2) it encodes using a dynamically updated dictionary allowing adaptation ...
doi:10.47893/ijpsoem.2011.1019
fatcat:gkjbzbg7nvelbat33wnhdqndkm
A Code Compression Method to Cope with Security Hardware Overheads
2007
19th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD'07)
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In this paper we present a code compression method, the IBC-EI (Instruction Based Compression with Encryption and Integrity checking), tailored to provide integrity checking and encryption to secure processor-memory ...
For the Leon processor and a set of benchmarks from the Mediabench and MiBench suites the habitual overheads due to security trend to zero in comparison to a system without security neither compression ...
For the same block and cache line parameters, using dynamic dictionaries will always produce worst compression ratios. ...
doi:10.1109/sbac-pad.2007.40
dblp:conf/sbac-pad/NagpalS07
fatcat:t6femibknjafto3efond5avo2m
Adaptive and flexible dictionary code compression for embedded applications
2006
Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems - CASES '06
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We present a new view of dictionary code compression for moderately high-performance processors for embedded applications. ...
Finally, we also introduce dynamic dictionaries where the dictionary contents is considered to be part of the context of a process and show that the performance overhead of reloading the dictionary contents ...
Albera and Bahar [1] , shows that more energy is consumed by the instruction cache than in the data cache due to the higher access rate to the instruction cache. ...
doi:10.1145/1176760.1176776
dblp:conf/cases/BrorssonC06
fatcat:vslvyejsu5gvrcrtkncz4jbeha
The implementation and evaluation of dynamic code decompression using DISE
2005
ACM Transactions on Embedded Computing Systems
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Code compression coupled with dynamic decompression is an important technique for both embedded and general-purpose microprocessors. ...
Postfetch decompression, in which decompression is performed after the compressed instructions have been fetched, allows the instruction cache to store compressed code but requires a highly efficient decompression ...
ACKNOWLEDGMENTS The authors thank Vlad Petric for his help with the energy simulations and the anonymous reviewers for their insightful comments. ...
doi:10.1145/1053271.1053274
fatcat:q6zmkz5qufadjl5jzijulpsczy
Design and Implementation of a High-Performance Microprocessor Cache Compression Algorithm
2008
Data Compression Conference (DCC), Proceedings
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We present a lossless compression algorithm that has been designed for on-line memory hierarchy compression, and cache compression in particular. ...
Researchers have proposed using hardware data compression units within the memory hierarchies of microprocessors in order to improve performance, energy efficiency, and functionality. ...
The last row refers to the effective system-wide compression ratios for different algorithms based on the cache trace data set. ...
doi:10.1109/dcc.2008.90
dblp:conf/dcc/ChenYLDS08
fatcat:w6ryse6s7jagpdl23m2rq3ep5e
A DISE implementation of dynamic code decompression
2003
Proceedings of the 2003 ACM SIGPLAN conference on Language, compiler, and tool for embedded systems - LCTES '03
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Code compression coupled with dynamic decompression is an important technique for both embedded and general-purpose microprocessors. ...
DISE-based compression can reduce total energy consumption by 10% and the energy-delay product by as much as 20%. ...
The authors thank Vlad Petric for his help with the energy simulations and the anonymous reviewers for their comments. Amir Roth is supported by NSF CAREER award CCR-0238203. ...
doi:10.1145/780732.780765
dblp:conf/lctrts/CorlissLR03
fatcat:7atmjc7wkjcvtb4dgfzy5bz5qy
A DISE implementation of dynamic code decompression
2003
SIGPLAN notices
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Code compression coupled with dynamic decompression is an important technique for both embedded and general-purpose microprocessors. ...
DISE-based compression can reduce total energy consumption by 10% and the energy-delay product by as much as 20%. ...
The authors thank Vlad Petric for his help with the energy simulations and the anonymous reviewers for their comments. Amir Roth is supported by NSF CAREER award CCR-0238203. ...
doi:10.1145/780731.780765
fatcat:mhxadxdjpzdzvbjllisvnr52bi
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