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Dynamic Cache Reconfiguration for Soft Real-Time Systems

Weixun Wang, Prabhat Mishra, Ann Gordon-Ross
2012 ACM Transactions on Embedded Computing Systems  
This article presents a novel approach for implementing cache reconfiguration in soft real-time systems by efficiently leveraging static analysis during runtime to minimize energy while maintain the same  ...  It is a major challenge to introduce cache reconfiguration into real-time multitasking systems since dynamic analysis may adversely affect tasks with timing constraints.  ...  The contribution of this article is a novel scheduling aware dynamic cache reconfiguration technique for soft real-time systems.  ... 
doi:10.1145/2220336.2220340 fatcat:gdgovatdfnaorg7scliudjoa4y

SACR: Scheduling-Aware Cache Reconfiguration for Real-Time Embedded Systems

Weixun Wang, Prabhat Mishra, Ann Gordon-Ross
2009 2009 22nd International Conference on VLSI Design  
It is a major challenge to introduce cache reconfiguration into real-time embedded systems since dynamic analysis may adversely affect tasks with real-time constraints.  ...  This paper presents a novel approach for implementing cache reconfiguration in soft real-time systems by efficiently leveraging static analysis during execution to both minimize energy and maximize performance  ...  The contribution of this paper is a novel scheduling aware dynamic cache reconfiguration technique for soft real-time embedded systems.  ... 
doi:10.1109/vlsi.design.2009.66 dblp:conf/vlsid/WangMG09 fatcat:57q64l374zfy5ecghajrchpmpu

Dynamic Reconfiguration of Two-Level Caches in Soft Real-Time Embedded Systems

Weixun Wang, Prabhat Mishra
2009 2009 IEEE Computer Society Annual Symposium on VLSI  
This paper efficiently integrates cache reconfiguration in soft real-time systems with a unified two-level cache hierarchy.  ...  While cache reconfiguration is successful in desktop-based systems, it is not directly applicable in real-time systems due to timing constraints.  ...  This paper apply cache reconfiguration in soft real-time systems with a unified twolevel cache hierarchy.  ... 
doi:10.1109/isvlsi.2009.22 dblp:conf/isvlsi/WangM09 fatcat:etkmuy7kwvddpahxatub2b4cwq

Dynamic Reconfiguration of Two-Level Cache Hierarchy in Real-Time Embedded Systems

Weixun Wang, Prabhat Mishra
2011 Journal of Low Power Electronics  
This paper efficiently integrates cache reconfiguration in real-time systems with a unified two-level cache hierarchy.  ...  While cache reconfiguration is successful in desktop-based and embedded systems, it is not directly applicable in real-time systems due to timing constraints.  ...  RECONFIGURATION OF TWO-LEVEL CACHES In this section, we present our work on cache reconfiguration for soft real-time systems with a twolevel cache hierarchy.  ... 
doi:10.1166/jolpe.2011.1113 fatcat:qayer6yilfgurl3feyyutkwdyi

Reliability and energy-aware cache reconfiguration for embedded systems

Yuanwen Huang, Prabhat Mishra
2016 2016 17th International Symposium on Quality Electronic Design (ISQED)  
We propose two heuristic approaches for reliability-and energy-aware dynamic cache reconfiguration.  ...  Cache vulnerability due to soft errors is one of the reliability concerns in embedded systems.  ...  An efficient cache reconfiguration framework is proposed for energy optimization in soft real-time systems in [4] .  ... 
doi:10.1109/isqed.2016.7479220 dblp:conf/isqed/HuangM16 fatcat:xryybbdhbre4pni2k24onegpfe

Dynamic tuning of configurable architectures

Chen Huang, David Sheldon, Frank Vahid
2008 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis - CODES/ISSS '08  
Such dynamic tuning can improve application performance or energy. However, reconfiguring incurs a temporary performance cost.  ...  AWW improves a nondynamic approach on average by 6%, and by up to 30% in lowreconfiguration-time situations.  ...  To facilitate reproduction, comparison, and extension of this work, the complete datasets used in this paper are available at http://www.cs.ucr.edu/~vahid for an indefinite period of time.  ... 
doi:10.1145/1450135.1450158 dblp:conf/codes/HuangSV08 fatcat:6srdoygoczesvguyovuf6smzci

Reconfigurable cache for real-time MPSoCs: Scheduling and implementation

Gang Chen, Biao Hu, Kai Huang, Alois Knoll, Kai Huang, Di Liu, Todor Stefanov, Feng Li
2016 Microprocessors and microsystems  
In this paper, we present a reconfigurable cache architecture which supports dynamic cache partitioning at hardware level and a framework that can exploit cache management for real-time MPSoCs.  ...  The proposed reconfigurable cache allows cores to dynamically allocate cache resource with minimal timing overhead while guaranteeing strict cache isolation among the real-time tasks.  ...  We propose a parameterized reconfigurable cache architecture, so called dynamic partitioned cache memory, for real-time multi-core system and physically implement it on FPGA.  ... 
doi:10.1016/j.micpro.2015.11.020 fatcat:paful55lavd3rbabcz6x7uf2aa

Vision for liquid architecture

R.D. Chamberlain, R.K. Cytron, J.E. Fritts, J.W. Lockwood
2006 Proceedings 20th IEEE International Parallel & Distributed Processing Symposium  
Real-time systems include performance in their correctness criteria, and the penalties for not succeeding (i.e., missing a deadline) can range from minor inconvenience (for some soft real-time requirements  ...  ) to total system failure (for some hard real-time requirements).  ... 
doi:10.1109/ipdps.2006.1639583 dblp:conf/ipps/ChamberlainCFL06 fatcat:ep4ohctwqfg3lcpa3zlzyegd7i

A General Algorithm for Energy-Aware Dynamic Reconfiguration in Multitasking Systems

Weixun Wang, S Ranka, P Mishra
2011 2011 24th Internatioal Conference on VLSI Design  
While dynamic voltage scaling (DVS) techniques have been extensively studied for processor energy conservation, dynamic cache reconfiguration (DCR) for reducing cache energy consumption in multitasking  ...  System optimization techniques based on dynamic reconfiguration are widely adopted for energy conservation.  ...  Wang et al. applied DCR in soft real-time systems by utilizing static profiling information at runtime for both single level cache [4] and multiple level cache hierarchy [5] .  ... 
doi:10.1109/vlsid.2011.17 dblp:conf/vlsid/WangRM11 fatcat:5tkxvczoajc6fmhg2ddozvo6um

Reconfigurable and Evolvable Architecture for Autonomous on-board systems

Yuriy Shiyanovskii, Francis Wolff, Chris Papachristou, David McIntyre
2008 2008 IEEE National Aerospace and Electronics Conference  
This paper deals with the dedevices will be based on evolvable reconfigurations [2] which sign architecture of an autonomous on-board system and the development of a real-time scheduler for the adaptation  ...  Future generations of reconfigurable systems to changing environments.  ...  The on-board system is based on a self reconfigurable multiprocessor architecture with dynamic reconfiguration of Layer3 Real Time DS Kernels hardware and adaptable application software recently  ... 
doi:10.1109/naecon.2008.4806550 fatcat:k5czwvjwkbb2perij7usp7oa5y

Energy-aware dynamic reconfiguration algorithms for real-time multitasking systems

Weixun Wang, Sanjay Ranka, Prabhat Mishra
2011 Sustainable Computing: Informatics and Systems  
While dynamic voltage scaling (DVS) techniques have been extensively studied for processor energy conservation, dynamic cache reconfiguration (DCR) for reducing cache energy consumption in multitasking  ...  System optimization techniques based on dynamic reconfiguration are widely adopted for energy conservation.  ...  soft real-time systems and thus not applicable to our case.  ... 
doi:10.1016/j.suscom.2010.10.006 fatcat:5wnvzpcutvhuhh5cjp4dqfo2de

Domain Adaptive Processor Architectures [chapter]

Florian Fricke, Safdar Mahmood, Javier Hoffmann, Muhammad Ali, Keyvan Shahin, Michael Hübner, Diana Göhringer
2020 Technologien für die intelligente Automation  
A novel class of processors which provide more data throughput with a simultaneously tremendously reduced energy consumption are required as a backbone for these "Things".  ...  The ongoing megatrends in industry and academia like the Internet of Things (IoT), the Industrial Internet of Things (IIoT) and Cyber-Physical Systems (CPS) present the developers of modern computer architectures  ...  [Nav16] propose two online heuristics to improve overall computing performance targeting soft real-time systems.  ... 
doi:10.1007/978-3-662-59895-5_23 fatcat:c3rzfowftfh4ncjxsjsgzbpy4a

Designing next generation data-centers with advanced communication protocols and systems services

P. Balaji, K. Vaidyanathan, S. Narravula, H.-W. Jin, D.K. Panda
2006 Proceedings 20th IEEE International Parallel & Distributed Processing Symposium  
Together with raw performance, such data-centers also lack in efficient support for intelligent services, such as requirements for caching documents, managing limited physical resources, load-balancing  ...  On the other hand, the System Area Network (SAN) technology is making rapid advances during the recent years.  ...  For the advanced data-center services, we further present two specific services, namely, dynamic content caching and active resource adaptation and reconfiguration.  ... 
doi:10.1109/ipdps.2006.1639585 dblp:conf/ipps/BalajiVNJP06 fatcat:45vq7y2rdreqxdyh7u5w3hdqdq

A Novel Methodology for Task Distribution in Heterogeneous Reconfigurable Computing System

Mahendra Vucha, Arvind Rajawat
2015 International Journal of Embedded Systems and Applications  
Modern embedded systems are being modeled as Heterogeneous Reconfigurable Computing Systems (HRCS) where Reconfigurable Hardware i.e.  ...  The real time applications JPEG, OFDM transmitters are represented as task graph and then the task are distributed, statically as well dynamically, to the platform HRCS in order to evaluate the performance  ...  A methodology in [34] presented for building real time reconfigurable systems and they ensure that all the constraints of the applications are met.  ... 
doi:10.5121/ijesa.2015.5102 fatcat:bhqbfz76qzhjpa3lhcl2rjslju

Design of NIOS II Soft-Core based Partial Reconfiguration Controller in FPGA for MPSoC Design

S. Beulah Hemalatha
2015 Indian Journal of Science and Technology  
NIOS II soft-core processor is programmed as control processor to perform reconfiguration partially and also it manages the dynamic power optimization process.  ...  This work describes an effective approach for power reduction techniques in FPGA based Multiprocessor system-on-Chip (MPSoC) platform and it works on partial reconfiguration technique during runtime.  ...  The timing diagram in Figure 6 shows the timing analysis partial reconfiguration using NIOS II soft core processor. Chip planner view of the proposed system in shown in Figure 7 .  ... 
doi:10.17485/ijst/2015/v8i32/87600 fatcat:pd7mu4h4azb6jofrb4qpnfg7uu
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