A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2019; you can also visit the original URL.
The file type is application/pdf.
Filters
An efficient multiple precision floating-point Multiply-Add Fused unit
2016
Microelectronics Journal
Preserved Fulltext
The MAF architecture features a dual-path organization reducing the latency of the floating-point add (FADD) instruction and utilizes the minimum number of operating components to keep the area low. ...
The objective of this paper is to present a multi-functional, multiple precision floating-point Multiply-Add Fused (MAF) unit. ...
In [29] two architectures performing dual-mode floating-point addition are presented. ...
doi:10.1016/j.mejo.2015.10.012
fatcat:phnyeunqpnaezfw7j3pcwu5kom
Design and Synthesis of Restoring Technique Based Dual Mode Floating Point Divider for Fast Computing Applications
2018
International Journal of Engineering & Technology
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2019; you can also visit the original URL.
The file type is application/pdf.
This paper relies on the dual-mode practicality of floating point division. ...
The proposed designed architecture supports the single precision (32-bit) as well as double precision (64-bit) IEEE 754 floating point format. ...
A Modified Radix-4 Booth Multiplier having a dual-mode feature is employed for the dual-mode fraction part division. ...
doi:10.14419/ijet.v7i3.6.14936
fatcat:63eyktu7arhfldf4ti5qusgpha
Merged Floating Point Multipliers
2019
International Journal of Engineering and Advanced Technology
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2020; you can also visit the original URL.
The file type is application/pdf.
Hence floating point multipliers became one of the research criteria. ...
Floating point multipliers are extensively used in many scientific and signal processing computations, due to high speed and memory requirements of IEEE-754 floating point multipliers which prevents its ...
An area and power efficient repetitive floating point multiplier architecture and implemented on a FPGA device with pipelined operations. This architecture reinforces both SP and DP operations [8] . ...
doi:10.35940/ijeat.a1042.1291s52019
fatcat:sjqkou6no5bvzcowkbon6uew3i
Improved Architectures for Fused Floating Point Add-Subtract Unit
2015
International Journal of Science and Research (IJSR)
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2022; you can also visit the original URL.
The file type is application/pdf.
The fused floating point add-subtract unit is useful for digital signal processing (DSP) applications Such as fast Fourier transform (FFT) & discrete cosine transform (DCT) butterfly operations. ...
The dual path design reduces latency compared to discrete design with area and power consumption between discrete and fused design. ...
Traditional Floating Point Add-subtract Unit A direct way to implement the floating-point add-subtract operation is to use two identical floating-point adders in parallel as shown in Fig. 2 . ...
doi:10.21275/v4i12.nov152018
fatcat:zid6ch4hgff3thbkb47q2ijtua
An Efficient Multi-Precision Floating Point Adder and Multiplier
2015
Indian Journal of Science and Technology
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2018; you can also visit the original URL.
The file type is application/pdf.
The floating point additions and multiplications are core operations in complex multiplication, in which inputs should be given in IEEE 754 standard formats. ...
The proposed floating point multiplier makes use of Vedic multiplication algorithm, because in array multiplication sharing of multiplication is not possible. ...
DPdSP Adder Architecture The present design of DPdSP Adder architecture has been designed for the support of the dual mode operation. ...
doi:10.17485/ijst/2015/v8i25/80236
fatcat:lv2yfbe24bg5dalvayedybkywu
Configurable Architectures for Multi-Mode Floating Point Adders
2015
IEEE Transactions on Circuits and Systems Part 1: Regular Papers
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
This paper presents two architectures for floating point (FP) adders, which operates in multi-mode configuration with multi-precision support. ...
First architecture (named QPdDP) works in dual-mode which can operates either for quadruple precision or two-parallel double precision. ...
This paper is extending the idea of dual-mode DPdSP adder architecture to the dual-mode QPdDP (quadruple precision with dual/two-parallel double precision) adder architecture. ...
doi:10.1109/tcsi.2015.2452351
fatcat:wzvb3f5vv5flxjrgneyujem32u
Introducing the Intel i860 64-bit microprocessor
1989
IEEE Micro
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
Pipelining also takes place in a dual-operation mode in which an add and a multiply process in parallel. ...
The four specialpurpose registers are used with the dual-operation floating-point instructions (described later). ...
His interests include processor architecture and system design. Margulls received his degree in electrical engineering from the University of Vermont in Burlington. ...
doi:10.1109/40.31485
fatcat:akcyrrrdvrgv3ggshiah77ygji
Configurable Architecture for Double/Two-Parallel Single Precision Floating Point Division
2014
2014 IEEE Computer Society Annual Symposium on VLSI
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2020; you can also visit the original URL.
The file type is application/pdf.
Compared to a standalone double precision divider, the proposed dual mode unified architecture needs ≈ 7% extra hardware, with ≈ 5% delay overhead. ...
Key components involved in the floating point division architecture are re-designed in order to efficiently enable the resource sharing and tune the data-path for processing both precision operands with ...
PROPOSED DPDSP DIVISION ARCHITECTURE The proposed floating point division architecture for double precision with dual (two-parallel) single precision support (DPdSP) is shown in Fig. 1 . ...
doi:10.1109/isvlsi.2014.45
dblp:conf/isvlsi/JaiswalCBP14
fatcat:s3fky2x7y5awvi4fy4zo73nmki
An Effective Implementation of Dual Path Fused Floating-Point Add-Subtract Unit for Reconfigurable Architectures
2017
International Journal of Intelligent Engineering and Systems
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2018; you can also visit the original URL.
The file type is application/pdf.
In this paper, an effective implementation of Fused Floating-point Add-Subtract (FFAS) unit with a modification in dual path design is presented. ...
The floating point operations are used in most of the signal processing applications that require high precision and good accuracy. ...
Discrete and Fused Floating-point Add-Subtract Units The Floating-point Add-Subtract (FAS) operation can be implemented using two identical FFASs in parallel [9] . ...
doi:10.22266/ijies2017.0430.05
fatcat:zv5orzi6fvckhmyx3mv242gznq
Low Power High Performance Analysis For 64 Bit Arithmetical Logical Unit
2016
Zenodo
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2020; you can also visit the original URL.
The file type is application/pdf.
These 64 bit ALU is identify input bit and according to that it will perform operation. Due to these logic we can save power consumption. ...
This project proposed an architecture of 64 bit General Purpose ALU .The critical power dissipation can be avoided by the application of clock gating of the hardware required and improving architectural ...
Akka 2008 [14] : According to this paper hands, Akkas presented architectures for dual mode adders and multipliers in floating-point [14, 15] , This paper presents dual-mode floating-point adder architectures ...
doi:10.5281/zenodo.52497
fatcat:fabncgmnfzbrzkt4efb4vaq7vy
Comparative Review of Floating-Point Multiplier Systems
2019
International Journal of Hybrid Information Technology
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2020; you can also visit the original URL.
The file type is application/pdf.
The study focuses on single, double, quadruple and multi-precision floating point multiplier architectures and seeks to identify engineering techniques involved in their development. ...
This paper presents a comprehensive comparative review of existing floating-point multiplier systems. ...
The third architecture (Double Precision Dual Single Precision Multiplier -DPdSP) was responsible for performing either single or double precision floating-point operation. ...
doi:10.21742/ijhit.2019.12.2.04
fatcat:slus7fyv2ffe7nezl3nivp5hke
Applications of Small-Scale Reconfigurability to Graphics Processors
[chapter]
2006
Lecture Notes in Computer Science
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
SSR is a relatively new architectural technique wherein functionality common to multiple subunits is reused rather than replicated, yielding high-performance reconfigurable hardware with reduced area requirements ...
fragment shader performance with a minimal impact on chip area. ...
A dual-mode floating point unit is a small-scale reconfigurable unit capable of performing two simultaneous single-precision operations or one double-precision opera-tion. ...
doi:10.1007/11802839_14
fatcat:leazm3pcefgypcwjdudc2peona
Implementation of Fast and Efficient Mac Unit on FPGA
2016
International Journal of Mathematical Sciences and Computing
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2018; you can also visit the original URL.
The file type is application/pdf.
Floating-point arithmetic operations on digital systems have become an important aspect of research in recent times. ...
In the proposed approach a fast and area efficient Carry Select Adder are implemented along with the parallel processing of various units used in the architecture. ...
In this paper, 3 path frameworks utilizes parallel path which is same as in dual path floating adders. The novel bridge framework utilizes floating-point elements to add a FMA instruction. ...
doi:10.5815/ijmsc.2016.04.03
fatcat:qpsjx2t43fd3xgvxzavttffpda
Design and Performance Analysis of Fixed-point Jacobi SVD Algorithm on Reconfigurable System
2014
Information Engineering Research Institute procedia
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2019; you can also visit the original URL.
The file type is application/pdf.
To achieve improved performance, SVD is implemented in reconfigurable system with parallel architecture. ...
It also analyses the performance of the architecture with respect to floating-point and SystemC fixed-point implementation based on number of accurate fractional bits, signal-to-quantization-noise-ratio ...
doi:10.1016/j.ieri.2014.08.005
fatcat:cvw7kcxhvrevlf3zer75wgmykm
Design and Test of Fixed-point Multimedia Co-processor for Mobile Applications
2006
Proceedings of the Design Automation & Test in Europe Conference
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
The fixed-point co-processor architecture with dual operations realizes advanced 3-D graphics algorithms and various streaming multimedia functions in a single hardware while consuming low power. ...
The instruction-wise clock gating on fixed-point SIMD datapath allows fine-grained power control in application-specific manner. ...
In addition, the fixed-point multiplier consumed only 83% power of the floating-point multiplier at the same operating frequency. ...
doi:10.1109/date.2006.243934
dblp:conf/date/SohnWYY06
fatcat:py2qih2dsbeobm3gxn3acrjyqq
« Previous
Showing results 1 — 15 out of 6,891 results