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What Your DRAM Power Models Are Not Telling You: Lessons from a Detailed Experimental Study [article]

Saugata Ghose, Abdullah Giray Yağlıkçı, Raghav Gupta, Donghyuk Lee, Kais Kudrolli, William X. Liu, Hasan Hassan, Kevin K. Chang, Niladrish Chatterjee, Aditya Agrawal, Mike O'Connor, Onur Mutlu
2018 arXiv   pre-print
Main memory (DRAM) consumes as much as half of the total system power in a computer today, resulting in a growing need to develop new DRAM architectures and systems that consume less power.  ...  This research was supported in part by the Semiconductor Research Corporation and the National Science Foundation (grants 1212962 and 1320531).  ...  Thanks to Naveen Kakarla for his assistance with the experimental validation of VAMPIRE.  ... 
arXiv:1807.05102v1 fatcat:onfrkogf7ba75hkgncmr6f7i6u

Architectural Techniques to Enhance DRAM Scaling

Yoongu Kim
For decades, main memory has enjoyed the continuous scaling of its physical substrate: DRAM (Dynamic Random Access Memory).  ...  This thesis identifies two specific challenges to DRAM scaling, and presents architectural techniques to overcome them.First, DRAM cells are becoming less reliable.  ...  This happens in two steps. First, the wordline corresponding to the currently activated row is lowered to zero voltage, disconnecting the cells from the bitlines.  ... 
doi:10.1184/r1/7461695.v1 fatcat:5pq46o5y7fghbpwsgu5wjrnyqe