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Driver modeling and alignment for worst-case delay noise

Supamas Sirichotiyakul, David Blaauw, Chanhee Oh, Rafi Levy, Vladimir Zolotov, Jingyan Zuo
2001 Proceedings of the 38th conference on Design automation - DAC '01  
We show that the worst case alignment of an aggressor net transition is a function of the receiver gate output loading, victim transition edge rate, and the noise pulse width and height and hence propose  ...  a pre-characterization approach to efficiently predict the worst-case alignment.  ...  Aggressor Alignment for Worst-Case Delay The interconnect and receiver delay are strongly dependent on how the noise waveforms are aligned with respect to the victim transition.  ... 
doi:10.1145/378239.379054 dblp:conf/dac/SirichotiyakulBOLZZ01 fatcat:rzarmwgca5hylbggali7r7g7sm

Driver modeling and alignment for worst-case delay noise

D. Blaauw, S. Sirichotiyakul, C. Oh
2003 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
We show that the worst case alignment of an aggressor net transition is a function of the receiver gate output loading, victim transition edge rate, and the noise pulse width and height and hence propose  ...  a pre-characterization approach to efficiently predict the worst-case alignment.  ...  Aggressor Alignment for Worst-Case Delay The interconnect and receiver delay are strongly dependent on how the noise waveforms are aligned with respect to the victim transition.  ... 
doi:10.1109/tvlsi.2002.808448 fatcat:lacfqvujnvgqvlkhxyql6mlubm

Driver modeling and alignment for worst-case delay noise

S. Sirichotiyakul, D. Blaauw, Chanhee Oh, R. Levy, V. Zolotov, Jingyan Zuo
Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232)  
We show that the worst case alignment of an aggressor net transition is a function of the receiver gate output loading, victim transition edge rate, and the noise pulse width and height and hence propose  ...  a pre-characterization approach to efficiently predict the worst-case alignment.  ...  Aggressor Alignment for Worst-Case Delay The interconnect and receiver delay are strongly dependent on how the noise waveforms are aligned with respect to the victim transition.  ... 
doi:10.1109/dac.2001.935600 fatcat:tp6v2zyhg5azvikksydbudg6pe

Timed pattern generation for noise-on-delay calculation

Seung Hoon Choi, Kaushik Roy, Florentin Dartu
2002 Proceedings - Design Automation Conference  
The worst-case delay in the presence of noise is predicted within 5% error for more than 99% of the cases tested using an average of 1.27 simulations per stage transition.  ...  We propose a solution that predicts the alignment of aggressor signals with respect to the victim signal to induce the worst-case noise effect on delay.  ...  The worst-case delay and the corresponding signal alignment analysis based on a linear driver model [10] , [11] has been very attractive for its simplicity although it can bring about inaccuracy.  ... 
doi:10.1145/513918.514133 dblp:conf/dac/ChoiRD02 fatcat:vehwoberbnclvobmsojbaw42be

Timed pattern generation for noise-on-delay calculation

Seung Hoon Choi, F. Dartu, K. Roy
2002 Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324)  
The worst-case delay in the presence of noise is predicted within 5% error for more than 99% of the cases tested using an average of 1.27 simulations per stage transition.  ...  We propose a solution that predicts the alignment of aggressor signals with respect to the victim signal to induce the worst-case noise effect on delay.  ...  The worst-case delay and the corresponding signal alignment analysis based on a linear driver model [10] , [11] has been very attractive for its simplicity although it can bring about inaccuracy.  ... 
doi:10.1109/dac.2002.1012744 fatcat:zhtsqwbnfrdxbfefsehuwatx2a

Timed pattern generation for noise-on-delay calculation

Seung Hoon Choi, Kaushik Roy, Florentin Dartu
2002 Proceedings - Design Automation Conference  
The worst-case delay in the presence of noise is predicted within 5% error for more than 99% of the cases tested using an average of 1.27 simulations per stage transition.  ...  We propose a solution that predicts the alignment of aggressor signals with respect to the victim signal to induce the worst-case noise effect on delay.  ...  The worst-case delay and the corresponding signal alignment analysis based on a linear driver model [10] , [11] has been very attractive for its simplicity although it can bring about inaccuracy.  ... 
doi:10.1145/514130.514133 fatcat:zkiij23655fatpiiuadpbuwnti

Determination of worst-case aggressor alignment for delay calculation

Paul D. Gross, Ravishankar Arunachalam, Karthik Rajagopal, Lawrence T. Pileggi
1998 Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design - ICCAD '98  
In this paper, we propose a new waveform iteration strategy to compute the delay in the presence of coupling and to align aggressor inputs to determine the worst-case victim delay.  ...  In timing analysis, the worst-case delay of gates along a critical path must include the effect of noise due to switching of nearby aggressor gates.  ...  Observe that aggressor alignment for worst-case delay at the drivers does not correspond to aggressor alignment for worst-case delay at the fanout nodes.  ... 
doi:10.1145/288548.288616 dblp:conf/iccad/GrossARP98 fatcat:w3d4aifivrhn5gjjgzdq2ei63e

Aggressor alignment for worst-case coupling noise

Lauren Hui Chen, Malgorzata Marek-Sadowska
2000 Proceedings of the 2000 international symposium on Physical design - ISPD '00  
In the second case we assume that timing windows are given for each aggressor input. We propose a simple procedure to find aggressor alignment for worst-case coupling in both cases.  ...  In this paper we study signal alignment resulting in maximum peak interconnect crosstalk noise. We consider two cases.  ...  ACKNOWLEDGMENTS This work was supported in part by the NSF grant CCR 9811528 and by Micro through Conexant Systems and Mentor Graphics.  ... 
doi:10.1145/332357.332373 dblp:conf/ispd/ChenM00 fatcat:2b36iov2wngcnjy6snpmgxdjpm

TACO

Ravishankar Arunachalam, Karthik Rajagopal, Lawrence T. Pileggi
2000 Proceedings of the 37th conference on Design automation - DAC '00  
The methodology utilizes a coupled Ceff gate model for capturing the provably worst-and bestcase delays as a function of the timing-window inputs to the gates.  ...  This paper introduces TACO, a timing analysis methodology that produces tight bounds on worst-and best-case timing for circuits with dominant coupling capacitance.  ...  Acknowledgments The authors would like to thank Alex Suess and Khalid Rahmat from IBM EDA, Fishkill for their help and support in the implementation of TACO in Einstimer and for providing test-case examples  ... 
doi:10.1145/337292.337415 dblp:conf/dac/ArunachalamRP00 fatcat:es6lgt4pinaq3dkivbtz7b4n6m

Noise propagation and failure criteria for VLSI designs

V. Zolotov, D. Blaauw, S. Sirichotiyakul, M. Becer, C. Oh, R. Panda, A. Grinshpon, R. Levy
2002 Computer-Aided Design (ICCAD), IEEE International Conference on  
We therefore propose a new linear model that accurately combines propagated and injected noise on a net and which maintains the efficiency of linear simulation.  ...  that are unstable and do not allow sufficient margin for error in the analysis.  ...  Hence, they can be computed independently and their worst-case alignment is easily determined.  ... 
doi:10.1145/774572.774659 dblp:conf/iccad/ZolotovBSBOPGL02 fatcat:x2dhkrucg5eyphv7by45zhhwfi

An efficient current-based logic cell model for crosstalk delay analysis

Debasish Das, William Scott, Shahin Nazarian, Hai Zhou
2009 2009 10th International Symposium on Quality of Electronic Design  
A current-based model for CMOS logic cells is presented which can be used for effective crosstalk noise and delta delay analysis in CMOS VLSI circuits.  ...  Logic Cell modeling is an important component in the analysis and design of CMOS integrated circuits, mostly due to nonlinear behavior of CMOS cells with respect to the voltage signal at their input and  ...  [3] applied a convex algorithm for worst case alignment computation in multiple aggressor case.  ... 
doi:10.1109/isqed.2009.4810367 dblp:conf/isqed/DasSNZ09 fatcat:nhmzaxwi6rgyhdlbgvrgu227bi

An efficient current-based logic cell model for crosstalk delay analysis

Shahin Nazarian, Debasish Das
2013 International journal of electronics (Print)  
A current-based model for CMOS logic cells is presented which can be used for effective crosstalk noise and delta delay analysis in CMOS VLSI circuits.  ...  Logic Cell modeling is an important component in the analysis and design of CMOS integrated circuits, mostly due to nonlinear behavior of CMOS cells with respect to the voltage signal at their input and  ...  [3] applied a convex algorithm for worst case alignment computation in multiple aggressor case.  ... 
doi:10.1080/00207217.2012.713015 fatcat:geoupfwkybhtxkmyyen35qo36i

Statistical gate delay calculation with crosstalk alignment consideration

Andrew B. Kahng, Bao Liu, Xu Xu
2006 Proceedings of the 16th ACM Great Lakes symposium on VLSI - GLSVLSI '06  
We establish a functional relationship between driver gate delay and crosstalk alignment by deterministic circuit simulation, and derive closed form formulas for statistical distributions of driver gate  ...  We study gate delay variation caused by crosstalk aggressor alignment, i.e., difference of signal arrival times in coupled neighboring interconnects.  ...  Finding the worst case crosstalk aggressor alignment which leads to the maximum/minimum gate delay is still open in deterministic timing analysis, although finding the worst case crosstalk aggressor alignment  ... 
doi:10.1145/1127908.1127961 dblp:conf/glvlsi/KahngLX06 fatcat:dkvyupcsxrcdplz6ltn5yqimhq

A noise-driven effective capacitance method with fast embedded noise rule calculation for functional noise analysis

Haihua Su, D. Widiger, C. Kashyap, F. Liu, B. Krauter
2005 Proceedings. 42nd Design Automation Conference, 2005.  
In addition, the linear driver model can significantly ease the task of finding the worst-case peak alignment among all the victim and aggressor noise sources.  ...  We present a noise-driven effective capacitance method for estimating the combined propagation noise and crosstalk noise.  ...  Two general approaches have been proposed for victim driver modeling and worst-case noise analysis.  ... 
doi:10.1109/dac.2005.193798 fatcat:ivpwxabgn5b2xcavgzr6umrkqa

A noise-driven effective capacitance method with fast embedded noise rule calculation for functional noise analysis

Haihua Su, David Widiger, Chandramouli Kashyap, Frank Liu, Byron Krauter
2005 Proceedings of the 42nd annual conference on Design automation - DAC '05  
In addition, the linear driver model can significantly ease the task of finding the worst-case peak alignment among all the victim and aggressor noise sources.  ...  We present a noise-driven effective capacitance method for estimating the combined propagation noise and crosstalk noise.  ...  Two general approaches have been proposed for victim driver modeling and worst-case noise analysis.  ... 
doi:10.1145/1065579.1065630 dblp:conf/dac/SuWKLK05 fatcat:4tag2yrikjapjby4blifroxdvq
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