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Distributed Test Using Logical Clock [chapter]

Young Joon Choi, Hee Yong Youn, Soonuk Seol, Sang Jo Yoo
<i title="Kluwer Academic Publishers"> Formal Techniques for Networked and Distributed Systems </i> &nbsp;
events, control-observation problem distributed testing, logical clock, output-shifting faults, test sequence 1.  ...  In this paper, we propose a formal test sequence generation algorithm using logical clock to control concurrent events.  ...  CONCLUSION AND FUTURE WORK In this paper, a LTS generation algorithm has been proposed to test a distributed system using logical clock.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1007/0-306-47003-9_5">doi:10.1007/0-306-47003-9_5</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/xderjtftsfgczdcd3unq4gsjte">fatcat:xderjtftsfgczdcd3unq4gsjte</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170912151445/https://link.springer.com/content/pdf/10.1007%2F0-306-47003-9_5.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/29/52/2952207e1c5dcc3e70976611aee1993484dce595.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1007/0-306-47003-9_5"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> Publisher / doi.org </button> </a>

An On-Chip Test Clock Control Scheme for Circuit Aging Monitoring

Hyunbean Yi
<span title="2013-02-28">2013</span> <i title="The Institute of Electronics Engineers of Korea"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/pdhhinwb6zdunc5juvdlqkgbdq" style="color: black;">JSTS Journal of Semiconductor Technology and Science</a> </i> &nbsp;
We describe limitations of existing at-speed test clock control methods and present an on-chip faster-than-at-speed test clock control scheme for intra/inter-clock domain test.  ...  Aging can be monitored by performing a delay test at faster clocks than functional clock in field and checking the current delay state from the test clock frequencies at which the delay test is passed  ...  During on-line test mode, the programmed clock (pclk) generated from the ODCS logic is used as the test clock.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.5573/jsts.2013.13.1.071">doi:10.5573/jsts.2013.13.1.071</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/64zoukh5vbdgpho2mh6pvdykam">fatcat:64zoukh5vbdgpho2mh6pvdykam</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170705234120/http://ocean.kisti.re.kr/downfile/volume/ieek/E1STAN/2013/v13n1/E1STAN_2013_v13n1_71.pdf?origin%3Dpublication_detail" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/7b/43/7b43484ac46e1d3cda4dc51e44d3f8274bfad4f4.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.5573/jsts.2013.13.1.071"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> Publisher / doi.org </button> </a>

Design methodology of a 200MHz superscalar microprocessor

Toshihiro Hattori, Yusuke Nitta, Mitsuho Seki, Susumu Narita, Kunio Uchiyama, Tsuyoshi Takahashi, Ryuichi Satomura
<span title="">1998</span> <i title="ACM Press"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/5vn6yyeefbbxtoo3uhwxwjwtme" style="color: black;">Proceedings of the 35th annual conference on Design automation conference - DAC &#39;98</a> </i> &nbsp;
Random test generation, logic emulation, and formal verification are applied to logic verification for shortening design time.  ...  Delay budgeting, forward / back annotation, and clock design are key features for timing driven design.  ...  In order to realize this complicated clock distribution logic, logic design and physical design of clocks are performed at the layout design phase.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/277044.277108">doi:10.1145/277044.277108</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/dac/HattoriNSNUTS98.html">dblp:conf/dac/HattoriNSNUTS98</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/g4z4wiwbufed3nqc6r6uc5fecq">fatcat:g4z4wiwbufed3nqc6r6uc5fecq</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170706151820/https://www.cs.york.ac.uk/rts/docs/SIGDA-Compendium-1994-2004/papers/1998/dac98/pdffiles/14_4.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/92/21/9221d81a1b5cbb1ece71bb36d8edd392b2c06191.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/277044.277108"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> acm.org </button> </a>

A true single-phase 8-bit adiabatic multiplier

Suhwan Kim, Conrad H. Ziesler, Marios C. Papaefthymiou
<span title="">2001</span> <i title="ACM Press"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/5vn6yyeefbbxtoo3uhwxwjwtme" style="color: black;">Proceedings of the 38th conference on Design automation - DAC &#39;01</a> </i> &nbsp;
Both the multiplier core and its built-in self-test logic have been designed using a true single-phase adiabatic logic family.  ...  Energy is supplied to the adiabatic circuitry via a sinusoidal power-clock waveform that is generated on-chip.  ...  The R T S V U b W Y X H voltage drop can be reduced even further by using wider clock distribution wires.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/378239.379061">doi:10.1145/378239.379061</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/dac/KimZP01.html">dblp:conf/dac/KimZP01</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/lddjxcvj7jhctmlwabbwydonpm">fatcat:lddjxcvj7jhctmlwabbwydonpm</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20030428055043/http://www.eecs.umich.edu:80/acal/adiabatic/papers/dac01.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/d7/f7/d7f7dc61c94fae339bb101cea59f39fe9ed5f4dd.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/378239.379061"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> acm.org </button> </a>

Optimised asynchronous timing for superconductive digital circuits

H.R. Gerber, C.J. Fourie, W.J. Perold
<span title="">2006</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/c2uwhfdohnb73djggo3fj6ekz4" style="color: black;">SAIEE Africa Research Journal</a> </i> &nbsp;
This paper describcs a ncw asynchronous self-liming schcmc whcre thc delails of clock distribution and clocking arc built inlo thc logic gates.  ...  Currcntly, synchronous clocking schcmcs outpcrform olhcr schcmcs, but with Ihc scalc of RSFQ circuits cvcr increasing. the proper use of liming schemes are becoming more crucial.  ...  Other differences include the use of pulse based logic rather than voltage state logic; the need for a clock signal for each logic gate and the fact that Josephson junction based circuits have a maximum  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.23919/saiee.2006.9487898">doi:10.23919/saiee.2006.9487898</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/fwwthjxqingb3lavliirm2poym">fatcat:fwwthjxqingb3lavliirm2poym</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20210829093927/https://ieeexplore.ieee.org/ielx7/8475037/9487886/09487898.pdf?tp=&amp;arnumber=9487898&amp;isnumber=9487886&amp;ref=" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/8d/f2/8df26dc231f5381aaea1c46715690e39b6f8e1b5.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.23919/saiee.2006.9487898"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> Publisher / doi.org </button> </a>

Design and Simulation of RSFQ/RISC Computer System

Zhong-Hai Zhang, Boran Guan
<span title="">2005</span> <i title="PIERS Enterprise"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/hicfaf3usfdrdjgmfrxhc6ea6m" style="color: black;">PIERS Online</a> </i> &nbsp;
According to the scheme, the timing signal of the logic module is generated by a test logic module.  ...  With this asynchronous approach, data is transferred in a delay-insensitive fashion to avoid the overhead of global clock distribution and the timing uncertainty.  ...  During the RSFQ chip programming, we have to pay much attention to the clock distribution, otherwise we will obtain the unexpected logic function with a lot of uncertainties.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.2529/piers041208100628">doi:10.2529/piers041208100628</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/ygpinlv6trd3rfhfivdapdsevq">fatcat:ygpinlv6trd3rfhfivdapdsevq</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20061005234542/http://emacademy.org/piers2k5zj/submit/get_fullpdf.php?status=valid&amp;id=041208100628&amp;pdffilename=041208100628.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/90/31/9031e004c1a35b1cb13d9da24e152bd573ee86b3.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.2529/piers041208100628"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> Publisher / doi.org </button> </a>

Probability aware fault-injection approach for SER estimation

Fabio B. Armelin, Lirida A. B. Naviner, Roberto d'Amore
<span title="">2018</span> <i title="IEEE"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/itagpu7yz5b77dljoflf6vcoea" style="color: black;">2018 IEEE 19th Latin-American Test Symposium (LATS)</a> </i> &nbsp;
For the example analyzed in this study, the use of relative fault probability decreases the number of logic blocks from 875 (adopting independent fault probability) to 495.  ...  SER estimation by radiation test is an accurate method, but it is expensive and requires the real device.  ...  For all fault-injection campaigns, the system clock was 40 MHz; the clock used to generate the transients was 40.1 MHz; the test vector sequence was 1,023 cycles (10-bit PRNG); the number of saboteurs  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/latw.2018.8349692">doi:10.1109/latw.2018.8349692</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/latw/ArmelinNd18a.html">dblp:conf/latw/ArmelinNd18a</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/phr73o4dfvdahc7oxlshcm4gum">fatcat:phr73o4dfvdahc7oxlshcm4gum</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20190430113608/http://plutao.sid.inpe.br/col/sid.inpe.br/plutao/2018/06.18.15.56/doc/armelin_probability.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/02/ea/02ea3d45bcbfb23a3ca3b020d1c18a707b24c717.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/latw.2018.8349692"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

27.6 An 821MHz 7.9Gb/s 7.3pJ/b/iteration charge-recovery LDPC decoder

Tai-Chuan Ou, Zhengya Zhang, Marios C. Papaefthymiou
<span title="">2014</span> <i title="IEEE"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/y4cu6znedbgxbdecknzpgfmoli" style="color: black;">2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC)</a> </i> &nbsp;
This paper presents a 576b LDPC decoder test-chip designed using a chargerecovery logic family.  ...  In terms of device count, this chip is more than an order of magnitude larger than the largest previously-reported chips with charge-recovery logic [3] [4] .  ...  A built-in-self-test (BIST) circuit that is used to generate and process the input and output of the decoder, along with RO, PG, and frequency-tuning circuits are implemented with static CMOS logic and  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/isscc.2014.6757514">doi:10.1109/isscc.2014.6757514</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/isscc/OuZP14.html">dblp:conf/isscc/OuZP14</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/sbroya3emzevjnh6yiquv7x4q4">fatcat:sbroya3emzevjnh6yiquv7x4q4</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170813155431/http://web.eecs.umich.edu/~zhengya/papers/isscc14_06757514.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/65/1c/651c49a0f1891edc0fe92a33a6cf7ff9321c0d65.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/isscc.2014.6757514"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

Clocked CMOS adiabatic logic with integrated single-phase power-clock supply

D. Maksimovic, V.G. Oklobdzija, B. Nikolic, K.W. Current
<span title="">2000</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/uqbr2omxsbdgtaxslmblka2nnu" style="color: black;">IEEE Transactions on Very Large Scale Integration (vlsi) Systems</a> </i> &nbsp;
The design and experimental evaluation of a clocked adiabatic logic (CAL) is described in this paper. CAL is a dual-rail logic that operates from a single-phase ac power-clock supply.  ...  This new low-energy logic makes it possible to integrate all power control circuitry on the chip, resulting in better system efficiency, lower cost, and simpler power distribution.  ...  Greneche for their help in layout and testing of the CAL chip.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/92.863629">doi:10.1109/92.863629</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/bcq7inlyxjdkrmrlbuqmzbck3u">fatcat:bcq7inlyxjdkrmrlbuqmzbck3u</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170813103514/https://people.eecs.berkeley.edu/~bora/Journals/2000/TVLSI00.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/c3/99/c399f29e709b6130ed9a9aeaf0c49dc47709fd5d.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/92.863629"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

Clocked CMOS adiabatic logic with integrated single-phase power-clock supply

Dragan Maksimović, Vojin G. Oklobdžija, Borivoje Nikolic, K. Wayne Current
<span title="">1997</span> <i title="ACM Press"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/qcoemsk4lfgznflartfnzb5rhy" style="color: black;">Proceedings of the 1997 international symposium on Low power electronics and design - ISLPED &#39;97</a> </i> &nbsp;
The design and experimental evaluation of a clocked adiabatic logic (CAL) is described in this paper. CAL is a dual-rail logic that operates from a single-phase ac power-clock supply.  ...  This new low-energy logic makes it possible to integrate all power control circuitry on the chip, resulting in better system efficiency, lower cost, and simpler power distribution.  ...  Greneche for their help in layout and testing of the CAL chip.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/263272.263365">doi:10.1145/263272.263365</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/islped/MaksimovicONC97.html">dblp:conf/islped/MaksimovicONC97</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/oje7yaanuvc23fh4qg2wjkv5jq">fatcat:oje7yaanuvc23fh4qg2wjkv5jq</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170813103514/https://people.eecs.berkeley.edu/~bora/Journals/2000/TVLSI00.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/c3/99/c399f29e709b6130ed9a9aeaf0c49dc47709fd5d.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/263272.263365"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> acm.org </button> </a>

Architecture issues and solutions for a high-capacity FPGA

Steve Trimberger, Khue Duong, Bob Conn
<span title="">1997</span> <i title="ACM Press"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/onq43wd7gna3zbic6lchssp6ke" style="color: black;">Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays - FPGA &#39;97</a> </i> &nbsp;
Others include interconnect performance, clock distribution and IO capacity. This paper describes these problems and the solutions to these problems chosen in the Xilinx XC4000EX family architecture.  ...  Two techniques were used to improve clocking. The first was obvious: improve the clock distribution on the chip with additional buffering and tuned distribution paths.  ...  One of the expected uses of the early clock buffer is in conjunction with a the low-skew clock buffer, where the same signal is input to both clock distribution trees.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/258305.258306">doi:10.1145/258305.258306</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/fpga/TrimbergerDC97.html">dblp:conf/fpga/TrimbergerDC97</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/fixf23wbf5a3hi2fetqiicb7xy">fatcat:fixf23wbf5a3hi2fetqiicb7xy</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170923044524/https://www.cs.york.ac.uk/rts/docs/SIGDA-Compendium-1994-2004/papers/1997/fpga97/pdffiles/01_1.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/39/a7/39a7ae3179f8e7d21d1e575cf85aa3cdf12157f9.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/258305.258306"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> acm.org </button> </a>

The physical attributes and testing aspects of the symbol system

B. E. Cowart, R. Rice, S. F. Lundstrom
<span title="">1971</span> <i title="ACM Press"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/4agqxjodzbejhgxmujtmvzj4t4" style="color: black;">Proceedings of the May 18-20, 1971, spring joint computer conference on - AFIPS &#39;71 (Spring)</a> </i> &nbsp;
Signal distribution Many signal distribution problems are encountered when using high speed circuits. 4 • 6 • 7 The choice of the CTpL logic family considerably reduces the problems of signal distribution  ...  The same test point panel and wing panels used for system testing mount on the board tester and are used to force and/or monitor logic conditions at the 200 signal pins and fifty test points on the boards  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/1478786.1478868">doi:10.1145/1478786.1478868</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/afips/CowartRL71.html">dblp:conf/afips/CowartRL71</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/kppn57ggnvf4phmmuqwwr2cif4">fatcat:kppn57ggnvf4phmmuqwwr2cif4</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170831020016/https://www.computer.org/csdl/proceedings/afips/1971/5077/00/50770589.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/a5/34/a534e042e84f0ffeead24b20bf7a8a7b3a872a4a.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/1478786.1478868"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> acm.org </button> </a>

Power-constrained high-frequency circuits for the IBM POWER6 microprocessor

B. Curran, E. Fluhr, J. Paredes, L. Sigal, J. Friedrich, Y.-H. Chan, C. Hwang
<span title="">2007</span> <i title="IBM"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/cr766v23pncdhc7hmikak4m7pi" style="color: black;">IBM Journal of Research and Development</a> </i> &nbsp;
This paper describes the circuit, physical design, clocking, timing, power, and hardware characterization challenges faced in the pursuit of this industryleading frequency.  ...  These layers are predominately used to distribute global power, global clocks, and I/O signal wires.  ...  For a more detailed discussion of clock distribution, refer to the section on global clock distribution.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1147/rd.516.0715">doi:10.1147/rd.516.0715</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/cjhusdggi5fyvamvmq74fqt4nm">fatcat:cjhusdggi5fyvamvmq74fqt4nm</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20110531201830/http://microblog.routed.net:80/wp-content/uploads/2007/11/2007curran-power-constrained-high-frequency-circuits-for-the-ibm-power6-microprocessor.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/29/4e/294e30972480c1af27ad7875136428bef5c8a418.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1147/rd.516.0715"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="unlock alternate icon" style="background-color: #fb971f;"></i> Publisher / doi.org </button> </a>

DFT timing design methodology for at-speed BIST

Yasuo Sato, Motoyuki Sato, Koki Tsutsumida, Masatoshi Kawashima, Kazumi Hatayama, Kazuyuki Nomoto
<span title="">2003</span> <i title="ACM Press"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/fkjmyf3l45eo5ovjdnpeqpdjd4" style="color: black;">Proceedings of the 2003 conference on Asia South Pacific design automation - ASPDAC</a> </i> &nbsp;
This paper presents a timing design methodology for at-speed BIST, using a multiple-clock domain scheme.  ...  Logic BIST is well known as an effective method for low cost testing.  ...  Logic BIST is well known as an effective method for low cost testing because it enables us to test a high-speed design chip with a low speed ATE.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/1119772.1119942">doi:10.1145/1119772.1119942</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/aspdac/SatoSTKHN03.html">dblp:conf/aspdac/SatoSTKHN03</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/5sw2dwdokrfjto4blwtc55ztgq">fatcat:5sw2dwdokrfjto4blwtc55ztgq</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170814154743/http://www.cecs.uci.edu/~papers/compendium94-03/papers/2003/aspdac03/pdffiles/08c_3.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/5e/c5/5ec58c74e72b9b77284d0b9107b1d666736408cf.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/1119772.1119942"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> acm.org </button> </a>

Functional Failure Rate Due to Single-Event Transients in Clock Distribution Networks

Thomas Lange, Maximilien Glorieux, Dan Alexandrescu, Luca Sterpone
<span title="">2019</span> <i title="IEEE"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/zg5te5xuqjc3pciymmuk7f7e6e" style="color: black;">2019 14th International Conference on Design &amp; Technology of Integrated Systems In Nanoscale Era (DTIS)</a> </i> &nbsp;
The approach is based on logic-level simulation and thus, only uses the register-transfer level description of a design.  ...  logic.  ...  Test Circuit, Testbench and Clock Distribution Network For this case-study the Ethernet 10GE MAC Core from OpenCores is used.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/dtis.2019.8735052">doi:10.1109/dtis.2019.8735052</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/dtis/LangeGAS19.html">dblp:conf/dtis/LangeGAS19</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/lqqplvslavgsphomdkdng5lhhe">fatcat:lqqplvslavgsphomdkdng5lhhe</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20200322102111/https://arxiv.org/pdf/2002.05455v1.pdf" title="fulltext PDF download [not primary version]" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <span style="color: #f43e3e;">&#10033;</span> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/dtis.2019.8735052"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>
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